DE69129668T2 - Verfahren zur Herstellung einer Halbleitervorrichtung mit einer bei niederer Temperatur ausgehärteten Epoxy-Vergussmasse - Google Patents

Verfahren zur Herstellung einer Halbleitervorrichtung mit einer bei niederer Temperatur ausgehärteten Epoxy-Vergussmasse

Info

Publication number
DE69129668T2
DE69129668T2 DE69129668T DE69129668T DE69129668T2 DE 69129668 T2 DE69129668 T2 DE 69129668T2 DE 69129668 T DE69129668 T DE 69129668T DE 69129668 T DE69129668 T DE 69129668T DE 69129668 T2 DE69129668 T2 DE 69129668T2
Authority
DE
Germany
Prior art keywords
epoxy
base
housing
package
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69129668T
Other languages
German (de)
English (en)
Other versions
DE69129668D1 (de
Inventor
Maurice S. Austin Texas 78759 Karpman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE69129668D1 publication Critical patent/DE69129668D1/de
Application granted granted Critical
Publication of DE69129668T2 publication Critical patent/DE69129668T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Adhesives Or Adhesive Processes (AREA)
DE69129668T 1990-03-23 1991-03-07 Verfahren zur Herstellung einer Halbleitervorrichtung mit einer bei niederer Temperatur ausgehärteten Epoxy-Vergussmasse Expired - Fee Related DE69129668T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/498,156 US5117279A (en) 1990-03-23 1990-03-23 Semiconductor device having a low temperature uv-cured epoxy seal

Publications (2)

Publication Number Publication Date
DE69129668D1 DE69129668D1 (de) 1998-08-06
DE69129668T2 true DE69129668T2 (de) 1999-03-11

Family

ID=23979815

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69129668T Expired - Fee Related DE69129668T2 (de) 1990-03-23 1991-03-07 Verfahren zur Herstellung einer Halbleitervorrichtung mit einer bei niederer Temperatur ausgehärteten Epoxy-Vergussmasse

Country Status (4)

Country Link
US (1) US5117279A (enExample)
EP (1) EP0447884B1 (enExample)
JP (1) JP3010784B2 (enExample)
DE (1) DE69129668T2 (enExample)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW332348B (en) * 1992-06-23 1998-05-21 Sony Co Ltd Manufacturing method for solid state motion picture device provides a highly accurate and low cost solid state motion picture device by use of empty package made of resin.
US5390082A (en) * 1992-07-06 1995-02-14 International Business Machines, Corp. Chip carrier with protective coating for circuitized surface
WO1994014193A1 (en) * 1992-12-09 1994-06-23 Olin Corporation Electronic package sealed with a dispensable adhesive
US5477008A (en) * 1993-03-19 1995-12-19 Olin Corporation Polymer plug for electronic packages
JPH0837252A (ja) * 1994-07-22 1996-02-06 Nec Corp 半導体装置
DE69528515T2 (de) * 1994-07-26 2003-04-24 Koninklijke Philips Electronics N.V., Eindhoven Herstellungsmethode eines oberflächen-montierbaren bauteils und dieser selbst
US6184575B1 (en) * 1994-08-26 2001-02-06 National Semiconductor Corporation Ultra-thin composite package for integrated circuits
WO1996034517A1 (en) * 1995-04-26 1996-10-31 Buztronics, Inc. Electronic novelty assembly including a pin switch and embedded printed circuit component
US7041771B1 (en) 1995-08-11 2006-05-09 Kac Holdings, Inc. Encapsulant with fluxing properties and method of use in flip-chip surface mount reflow soldering
US6426484B1 (en) 1996-09-10 2002-07-30 Micron Technology, Inc. Circuit and method for heating an adhesive to package or rework a semiconductor die
US5938956A (en) * 1996-09-10 1999-08-17 Micron Technology, Inc. Circuit and method for heating an adhesive to package or rework a semiconductor die
US5689089A (en) * 1996-09-20 1997-11-18 Motorola, Inc. Electronic control module having fluid-tight seals of a polymer material which expands when wet
US6274927B1 (en) 1999-06-03 2001-08-14 Amkor Technology, Inc. Plastic package for an optical integrated circuit device and method of making
JP4588837B2 (ja) * 2000-04-11 2010-12-01 浜松ホトニクス株式会社 半導体受光装置
US6432752B1 (en) * 2000-08-17 2002-08-13 Micron Technology, Inc. Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages
US7127362B2 (en) 2000-08-22 2006-10-24 Mundt Randall S Process tolerant methods and apparatus for obtaining data
JP4003860B2 (ja) * 2000-11-02 2007-11-07 富士通株式会社 マイクロアクチュエータ及びその製造方法
US6376266B1 (en) * 2000-11-06 2002-04-23 Semiconductor Components Industries Llc Semiconductor package and method for forming same
US6747298B2 (en) 2001-07-23 2004-06-08 Cree, Inc. Collets for bonding of light emitting diodes having shaped substrates
US6888167B2 (en) * 2001-07-23 2005-05-03 Cree, Inc. Flip-chip bonding of light emitting devices and light emitting devices suitable for flip-chip bonding
US6692610B2 (en) * 2001-07-26 2004-02-17 Osram Opto Semiconductors Gmbh Oled packaging
US6861720B1 (en) 2001-08-29 2005-03-01 Amkor Technology, Inc. Placement template and method for placing optical dies
US6759266B1 (en) * 2001-09-04 2004-07-06 Amkor Technology, Inc. Quick sealing glass-lidded package fabrication method
US7276394B2 (en) * 2001-09-20 2007-10-02 Eastman Kodak Company Large area flat image sensor assembly
US20030054583A1 (en) * 2001-09-20 2003-03-20 Eastman Kodak Company Method for producing an image sensor assembly
US6507097B1 (en) * 2001-11-29 2003-01-14 Clarisay, Inc. Hermetic package for pyroelectric-sensitive electronic device and method of manufacturing the same
US6784534B1 (en) 2002-02-06 2004-08-31 Amkor Technology, Inc. Thin integrated circuit package having an optically transparent window
JP3560161B1 (ja) * 2003-01-30 2004-09-02 日立化成工業株式会社 半導体封止用エポキシ樹脂組成物の製造方法
US7195953B2 (en) * 2003-04-02 2007-03-27 Yamaha Corporation Method of manufacturing a semiconductor package using a lead frame having through holes or hollows therein
DE102004013816A1 (de) * 2004-03-20 2005-10-06 Robert Bosch Gmbh Verfahren zum Herstellen eines Sensormoduls und Sensormodul
US7517728B2 (en) * 2004-03-31 2009-04-14 Cree, Inc. Semiconductor light emitting devices including a luminescent conversion element
EP1619726A1 (fr) * 2004-07-22 2006-01-25 St Microelectronics S.A. Boîtier optique pour capteur semiconducteur
KR100782798B1 (ko) * 2006-02-22 2007-12-05 삼성전기주식회사 기판 패키지 및 그 제조 방법
DE102006008793A1 (de) * 2006-02-24 2007-09-13 Osram Opto Semiconductors Gmbh Elektronisches Bauteil
EP2019424B1 (de) 2007-07-26 2016-11-23 SEMIKRON Elektronik GmbH & Co. KG Leistungshalbleitermodul mit Dichteinrichtung zum Substratträger und Herstellungsverfahren hierzu
US8421214B2 (en) * 2007-10-10 2013-04-16 Vishay General Semiconductor Llc Semiconductor device and method for manufacturing a semiconductor device
US9147813B2 (en) 2011-09-09 2015-09-29 Avago Technologies General Ip (Singapore) Pte. Ltd. High thermal conductivity and low degradation die attach with dual adhesive
WO2015092999A1 (ja) 2013-12-19 2015-06-25 株式会社大真空 電子部品用パッケージ及び圧電デバイス
US10170304B1 (en) 2017-10-25 2019-01-01 Globalfoundries Inc. Self-aligned nanotube structures

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4000054A (en) * 1970-11-06 1976-12-28 Microsystems International Limited Method of making thin film crossover structure
US4141055A (en) * 1977-04-27 1979-02-20 Bell Telephone Laboratories, Incorporated Crossover structure for microelectronic circuits
US4480009A (en) * 1980-12-15 1984-10-30 M&T Chemicals Inc. Siloxane-containing polymers
EP0114258A1 (en) * 1982-11-30 1984-08-01 Kabushiki Kaisha Toshiba Resin encapsulation type photo-semiconductor devices
US4524238A (en) * 1982-12-29 1985-06-18 Olin Corporation Semiconductor packages
US4703338A (en) * 1983-10-14 1987-10-27 Daicel Chemical Industries, Ltd. Resin composition to seal electronic device
US4783697A (en) * 1985-01-07 1988-11-08 Motorola, Inc. Leadless chip carrier for RF power transistors or the like

Also Published As

Publication number Publication date
EP0447884B1 (en) 1998-07-01
JP3010784B2 (ja) 2000-02-21
US5117279A (en) 1992-05-26
DE69129668D1 (de) 1998-08-06
EP0447884A2 (en) 1991-09-25
EP0447884A3 (enExample) 1994-02-23
JPH0621251A (ja) 1994-01-28

Similar Documents

Publication Publication Date Title
DE69129668T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung mit einer bei niederer Temperatur ausgehärteten Epoxy-Vergussmasse
DE69023091T2 (de) Gehäuse für in Plastik eingebettete integrierte Schaltungen und Herstellungsverfahren.
DE69209772T2 (de) Gehäuseanordnung für ein funktionales bauelement und herstellungsverfahren
DE69017918T2 (de) Verfahren zum verkapseln einer elektronischen anordnung mit leiterband und die packung dafür.
DE102010047646B4 (de) Harz-versiegelte elektronische Steuervorrichtung und Verfahren zur Herstellung derselben
DE19518753B4 (de) Halbleitervorrichtung und Verfahren zu ihrer Herstellung
DE102011053871B4 (de) Multichip-Halbleitergehäuse und deren Zusammenbau
DE69838597T2 (de) Lichtemittierende Halbleitervorrichtung und Herstellungsverfahren
DE10049288B4 (de) Elektronische Bauteile und eine Folienband zum Verpacken von Bonddrahtverbindungen elektronischer Bauteile sowie deren Herstellungsverfahren
DE4422216A1 (de) Mehrlagige metallische Leiterplatte und gegossener Baustein
DE69209482T2 (de) Elektronikverpackung mit erhöhter Wärmeableitung und Verfahren zu ihrer Herstellung
WO2011157522A1 (de) Oberflächenmontierbares optoelektronisches bauelement und verfahren zur herstellung eines oberflächenmontierbaren optoelektronischen bauelements
DE4329083A1 (de) Baugruppe zur Aufnahme elektronischer Bauelemente
DE102014213564A1 (de) Halbleitervorrichtung und Verfahren zu ihrer Herstellung
DE102008045581A1 (de) Halbleitervorrichtung und Herstellungsverfahren der Halbleitervorrichtung
DE4427309A1 (de) Herstellung eines Trägerelementmoduls zum Einbau in Chipkarten oder andere Datenträgerkarten
DE102004021927B4 (de) Verfahren zur inneren elektrischen Isolation eines Substrats für ein Leistungshalbleitermodul
DE10222608A1 (de) Halbleitervorrichtung und Verfahren zum Herstellen derselben
DE102017106407B4 (de) Verfahren zur Herstellung von optoelektronischen Halbleiterbauteilen
DE10232788B4 (de) Elektronisches Bauteil mit einem Halbleiterchip auf einem Systemträger, Systemträger und Verfahren zur Herstellung eines elektronischen Bauteils
DE69417329T2 (de) In Harz versiegelte Halbleiteranordnung
DE102009042921A1 (de) Halbleiterbauelement
DE102016124270A1 (de) Halbleiter-package und verfahren zum fertigen eines halbleiter-package
DE102006033175A1 (de) Elektronikanordnung
DE19640006B4 (de) Verfahren zum Herstellen eines elektronischen Bauelements

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee