DE69129404T2 - Speicherzelleschaltung und Matrix - Google Patents
Speicherzelleschaltung und MatrixInfo
- Publication number
- DE69129404T2 DE69129404T2 DE69129404T DE69129404T DE69129404T2 DE 69129404 T2 DE69129404 T2 DE 69129404T2 DE 69129404 T DE69129404 T DE 69129404T DE 69129404 T DE69129404 T DE 69129404T DE 69129404 T2 DE69129404 T2 DE 69129404T2
- Authority
- DE
- Germany
- Prior art keywords
- matrix
- memory cell
- cell circuit
- circuit
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
- G11C11/4023—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh using field effect transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/636,518 US5287304A (en) | 1990-12-31 | 1990-12-31 | Memory cell circuit and array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69129404D1 DE69129404D1 (de) | 1998-06-18 |
| DE69129404T2 true DE69129404T2 (de) | 1998-10-29 |
Family
ID=24552248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69129404T Expired - Fee Related DE69129404T2 (de) | 1990-12-31 | 1991-12-30 | Speicherzelleschaltung und Matrix |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5287304A (de) |
| EP (1) | EP0493830B1 (de) |
| JP (1) | JPH04340762A (de) |
| KR (1) | KR100205669B1 (de) |
| DE (1) | DE69129404T2 (de) |
| TW (1) | TW222705B (de) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4501164B2 (ja) * | 1998-05-01 | 2010-07-14 | ソニー株式会社 | 半導体記憶装置 |
| JP2009177200A (ja) * | 1998-05-01 | 2009-08-06 | Sony Corp | 半導体記憶装置 |
| US6418490B1 (en) * | 1998-12-30 | 2002-07-09 | International Business Machines Corporation | Electronic circuit interconnection system using a virtual mirror cross over package |
| US7372728B2 (en) * | 2004-06-16 | 2008-05-13 | Stmicroelectronics, Inc. | Magnetic random access memory array having bit/word lines for shared write select and read operations |
| FR2871921A1 (fr) * | 2004-06-16 | 2005-12-23 | St Microelectronics Sa | Architecture de memoire a lignes d'ecriture segmentees |
| US7209383B2 (en) * | 2004-06-16 | 2007-04-24 | Stmicroelectronics, Inc. | Magnetic random access memory array having bit/word lines for shared write select and read operations |
| US7301800B2 (en) * | 2004-06-30 | 2007-11-27 | Stmicroelectronics, Inc. | Multi-bit magnetic random access memory element |
| US7136298B2 (en) * | 2004-06-30 | 2006-11-14 | Stmicroelectronics, Inc. | Magnetic random access memory array with global write lines |
| US7079415B2 (en) * | 2004-06-30 | 2006-07-18 | Stmicroelectronics, Inc. | Magnetic random access memory element |
| US7106621B2 (en) * | 2004-06-30 | 2006-09-12 | Stmicroelectronics, Inc. | Random access memory array with parity bit structure |
| US7465973B2 (en) * | 2004-12-03 | 2008-12-16 | International Business Machines Corporation | Integrated circuit having gates and active regions forming a regular grating |
| US10109637B1 (en) * | 2017-12-28 | 2018-10-23 | Globalfoundries Inc. | Cross couple structure for vertical transistors |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3611317A (en) * | 1970-02-02 | 1971-10-05 | Bell Telephone Labor Inc | Nested chip arrangement for integrated circuit memories |
| US3638202A (en) * | 1970-03-19 | 1972-01-25 | Bell Telephone Labor Inc | Access circuit arrangement for equalized loading in integrated circuit arrays |
| US4184208A (en) * | 1978-07-19 | 1980-01-15 | Texas Instruments Incorporated | Pseudo-static semiconductor memory cell |
| JPS60136097A (ja) * | 1983-12-23 | 1985-07-19 | Hitachi Ltd | 連想メモリ装置 |
-
1990
- 1990-12-31 US US07/636,518 patent/US5287304A/en not_active Expired - Lifetime
-
1991
- 1991-12-27 JP JP3347004A patent/JPH04340762A/ja active Pending
- 1991-12-30 EP EP91122374A patent/EP0493830B1/de not_active Expired - Lifetime
- 1991-12-30 KR KR1019910025486A patent/KR100205669B1/ko not_active IP Right Cessation
- 1991-12-30 DE DE69129404T patent/DE69129404T2/de not_active Expired - Fee Related
-
1992
- 1992-04-28 TW TW081103297A patent/TW222705B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| EP0493830A2 (de) | 1992-07-08 |
| DE69129404D1 (de) | 1998-06-18 |
| KR920013465A (ko) | 1992-07-29 |
| EP0493830B1 (de) | 1998-05-13 |
| KR100205669B1 (ko) | 1999-07-01 |
| JPH04340762A (ja) | 1992-11-27 |
| EP0493830A3 (en) | 1993-01-27 |
| TW222705B (de) | 1994-04-21 |
| US5287304A (en) | 1994-02-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |