KR900005462A - 개량된 단일 이벤트 업셋 비율 감소회로를 갖고 있는 메모리 셀 - Google Patents

개량된 단일 이벤트 업셋 비율 감소회로를 갖고 있는 메모리 셀

Info

Publication number
KR900005462A
KR900005462A KR1019890012940A KR890012940A KR900005462A KR 900005462 A KR900005462 A KR 900005462A KR 1019890012940 A KR1019890012940 A KR 1019890012940A KR 890012940 A KR890012940 A KR 890012940A KR 900005462 A KR900005462 A KR 900005462A
Authority
KR
South Korea
Prior art keywords
event
memory cell
reduction circuit
rate reduction
improved single
Prior art date
Application number
KR1019890012940A
Other languages
English (en)
Other versions
KR0141517B1 (ko
Inventor
지 더블유 브레이크 테런스
더블유 휴스톤 씨어도르
Original Assignee
텍사스 인스트루먼츠 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/241,681 external-priority patent/US4912675A/en
Priority claimed from US07/241,524 external-priority patent/US4914629A/en
Priority claimed from US07/252,200 external-priority patent/US4956814A/en
Application filed by 텍사스 인스트루먼츠 인코포레이티드 filed Critical 텍사스 인스트루먼츠 인코포레이티드
Publication of KR900005462A publication Critical patent/KR900005462A/ko
Application granted granted Critical
Publication of KR0141517B1 publication Critical patent/KR0141517B1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information
KR1019890012940A 1988-09-07 1989-09-06 개량된 단일 이벤트 업셋 비율 감소회로를 갖고 있는 메모리 셀 KR0141517B1 (ko)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US07/241,681 US4912675A (en) 1988-09-07 1988-09-07 Single event upset hardened memory cell
US241,681 1988-09-07
US07/241,524 US4914629A (en) 1988-09-07 1988-09-07 Memory cell including single event upset rate reduction circuitry
US241,524 1988-09-07
US252,200 1988-09-30
US07/252,200 US4956814A (en) 1988-09-30 1988-09-30 Memory cell with improved single event upset rate reduction circuitry

Publications (2)

Publication Number Publication Date
KR900005462A true KR900005462A (ko) 1990-04-14
KR0141517B1 KR0141517B1 (ko) 1998-07-15

Family

ID=27399490

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890012940A KR0141517B1 (ko) 1988-09-07 1989-09-06 개량된 단일 이벤트 업셋 비율 감소회로를 갖고 있는 메모리 셀

Country Status (4)

Country Link
EP (1) EP0357982B1 (ko)
JP (1) JP2756316B2 (ko)
KR (1) KR0141517B1 (ko)
DE (1) DE68921394T2 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6275080B1 (en) 1999-07-28 2001-08-14 Bae Systems Enhanced single event upset immune latch circuit
JP2005302124A (ja) * 2004-04-09 2005-10-27 Seiko Epson Corp 半導体記憶装置
JP4655668B2 (ja) * 2005-02-23 2011-03-23 セイコーエプソン株式会社 強誘電体コンデンサラッチ回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3440444A (en) * 1965-12-30 1969-04-22 Rca Corp Driver-sense circuit arrangement

Also Published As

Publication number Publication date
KR0141517B1 (ko) 1998-07-15
JPH02210691A (ja) 1990-08-22
EP0357982A3 (en) 1990-12-05
EP0357982A2 (en) 1990-03-14
DE68921394T2 (de) 1995-06-29
EP0357982B1 (en) 1995-03-01
DE68921394D1 (de) 1995-04-06
JP2756316B2 (ja) 1998-05-25

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