DE68921394D1 - Speicherzelle mit einer Schaltung zur Reduzierung von Unordnungseinzelereignissen. - Google Patents

Speicherzelle mit einer Schaltung zur Reduzierung von Unordnungseinzelereignissen.

Info

Publication number
DE68921394D1
DE68921394D1 DE68921394T DE68921394T DE68921394D1 DE 68921394 D1 DE68921394 D1 DE 68921394D1 DE 68921394 T DE68921394 T DE 68921394T DE 68921394 T DE68921394 T DE 68921394T DE 68921394 D1 DE68921394 D1 DE 68921394D1
Authority
DE
Germany
Prior art keywords
circuit
memory cell
reducing individual
disorder events
individual disorder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68921394T
Other languages
English (en)
Other versions
DE68921394T2 (de
Inventor
Terence G W Blake
Theodore W Houston
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/241,524 external-priority patent/US4914629A/en
Priority claimed from US07/241,681 external-priority patent/US4912675A/en
Priority claimed from US07/252,200 external-priority patent/US4956814A/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE68921394D1 publication Critical patent/DE68921394D1/de
Application granted granted Critical
Publication of DE68921394T2 publication Critical patent/DE68921394T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
DE68921394T 1988-09-07 1989-08-08 Speicherzelle mit einer Schaltung zur Reduzierung von Unordnungseinzelereignissen. Expired - Fee Related DE68921394T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US07/241,524 US4914629A (en) 1988-09-07 1988-09-07 Memory cell including single event upset rate reduction circuitry
US07/241,681 US4912675A (en) 1988-09-07 1988-09-07 Single event upset hardened memory cell
US07/252,200 US4956814A (en) 1988-09-30 1988-09-30 Memory cell with improved single event upset rate reduction circuitry

Publications (2)

Publication Number Publication Date
DE68921394D1 true DE68921394D1 (de) 1995-04-06
DE68921394T2 DE68921394T2 (de) 1995-06-29

Family

ID=27399490

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68921394T Expired - Fee Related DE68921394T2 (de) 1988-09-07 1989-08-08 Speicherzelle mit einer Schaltung zur Reduzierung von Unordnungseinzelereignissen.

Country Status (4)

Country Link
EP (1) EP0357982B1 (de)
JP (1) JP2756316B2 (de)
KR (1) KR0141517B1 (de)
DE (1) DE68921394T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1203450A1 (de) 1999-07-28 2002-05-08 Lockheed Martin Corporation Verbesserte, gegen unordnungseinzelereignisse unempfindliche verriegelungsschaltung
JP2005302124A (ja) * 2004-04-09 2005-10-27 Seiko Epson Corp 半導体記憶装置
JP4655668B2 (ja) * 2005-02-23 2011-03-23 セイコーエプソン株式会社 強誘電体コンデンサラッチ回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3440444A (en) * 1965-12-30 1969-04-22 Rca Corp Driver-sense circuit arrangement

Also Published As

Publication number Publication date
DE68921394T2 (de) 1995-06-29
EP0357982A2 (de) 1990-03-14
JP2756316B2 (ja) 1998-05-25
EP0357982B1 (de) 1995-03-01
KR0141517B1 (ko) 1998-07-15
JPH02210691A (ja) 1990-08-22
EP0357982A3 (en) 1990-12-05
KR900005462A (ko) 1990-04-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee