DE69128464T2 - Halbleiteranordnung und ihr herstellungsverfahren - Google Patents

Halbleiteranordnung und ihr herstellungsverfahren

Info

Publication number
DE69128464T2
DE69128464T2 DE69128464T DE69128464T DE69128464T2 DE 69128464 T2 DE69128464 T2 DE 69128464T2 DE 69128464 T DE69128464 T DE 69128464T DE 69128464 T DE69128464 T DE 69128464T DE 69128464 T2 DE69128464 T2 DE 69128464T2
Authority
DE
Germany
Prior art keywords
production process
semiconductor arrangement
semiconductor
arrangement
production
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128464T
Other languages
English (en)
Other versions
DE69128464D1 (de
Inventor
Kazuto Fujitsu Limited Tsuji
Yoshiyuki Fujitsu Limit Yoneda
Junichi Fujitsu Limited Kasai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69128464D1 publication Critical patent/DE69128464D1/de
Publication of DE69128464T2 publication Critical patent/DE69128464T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
DE69128464T 1990-09-10 1991-09-09 Halbleiteranordnung und ihr herstellungsverfahren Expired - Fee Related DE69128464T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP23962290 1990-09-10
PCT/JP1991/001195 WO1992004730A1 (en) 1990-09-10 1991-09-09 Semiconductor device and its manufacturing process

Publications (2)

Publication Number Publication Date
DE69128464D1 DE69128464D1 (de) 1998-01-29
DE69128464T2 true DE69128464T2 (de) 1998-04-16

Family

ID=17047471

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128464T Expired - Fee Related DE69128464T2 (de) 1990-09-10 1991-09-09 Halbleiteranordnung und ihr herstellungsverfahren

Country Status (5)

Country Link
US (1) US5440170A (de)
EP (1) EP0503072B1 (de)
KR (1) KR960003853B1 (de)
DE (1) DE69128464T2 (de)
WO (1) WO1992004730A1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960000706B1 (ko) * 1993-07-12 1996-01-11 한국전기통신공사 전력소자용 플라스틱 패키지 구조 및 그 제조방법
TW270213B (de) * 1993-12-08 1996-02-11 Matsushita Electric Ind Co Ltd
US5532905A (en) * 1994-07-19 1996-07-02 Analog Devices, Inc. Thermally enhanced leadframe for packages that utilize a large number of leads
US5519576A (en) * 1994-07-19 1996-05-21 Analog Devices, Inc. Thermally enhanced leadframe
US5594234A (en) * 1994-11-14 1997-01-14 Texas Instruments Incorporated Downset exposed die mount pad leadframe and package
FR2732509B1 (fr) * 1995-03-31 1997-06-13 Sgs Thomson Microelectronics Boitier de montage d'une puce de circuit integre
JPH1065085A (ja) * 1996-06-28 1998-03-06 Siemens Ag パワーパッケージ内で使用するためのリードフレーム
JP2936062B2 (ja) * 1996-11-11 1999-08-23 富士通株式会社 半導体装置の製造方法
DE19808193B4 (de) * 1998-02-27 2007-11-08 Robert Bosch Gmbh Leadframevorrichtung und entsprechendes Herstellungsverfahren
JP3892139B2 (ja) * 1998-03-27 2007-03-14 株式会社ルネサステクノロジ 半導体装置
JP4523138B2 (ja) * 2000-10-06 2010-08-11 ローム株式会社 半導体装置およびそれに用いるリードフレーム
JP3418373B2 (ja) * 2000-10-24 2003-06-23 エヌ・アール・エス・テクノロジー株式会社 弾性表面波装置及びその製造方法
WO2007018473A1 (en) * 2005-08-05 2007-02-15 Infineon Technologies Ag Leadframe and semiconductor package
TW201251524A (en) * 2011-06-02 2012-12-16 Univ Nat Taipei Technology Circuit board with heat sink and method of fabricating the same
EP2790213A3 (de) 2013-04-11 2015-04-01 Chun Ho Fan Hohlraumgehäuse

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5676542A (en) * 1979-11-28 1981-06-24 Hitachi Ltd Resin-sealed semiconductor device
JPS5966157A (ja) * 1982-10-08 1984-04-14 Fujitsu Ltd 半導体装置及びその製造方法
JPS5979536A (ja) * 1982-10-29 1984-05-08 Nec Corp 樹脂封止型半導体装置
JPS5996757A (ja) * 1982-11-25 1984-06-04 Toshiba Corp 半導体装置
JPS59117141A (ja) * 1982-12-24 1984-07-06 Hitachi Ltd 半導体装置
JPS59175753A (ja) * 1983-03-25 1984-10-04 Toshiba Corp 半導体装置およびリ−ドフレ−ム
JPH0828447B2 (ja) * 1983-10-05 1996-03-21 富士通株式会社 半導体装置の製造方法
JPS61108160A (ja) * 1984-11-01 1986-05-26 Nec Corp コンデンサ内蔵型半導体装置及びその製造方法
US4918511A (en) * 1985-02-01 1990-04-17 Advanced Micro Devices, Inc. Thermal expansion compensated metal lead frame for integrated circuit package
US4884124A (en) * 1986-08-19 1989-11-28 Mitsubishi Denki Kabushiki Kaisha Resin-encapsulated semiconductor device
JPS6354759A (ja) * 1986-08-25 1988-03-09 Hitachi Micro Comput Eng Ltd 電子装置
US4942452A (en) * 1987-02-25 1990-07-17 Hitachi, Ltd. Lead frame and semiconductor device
JPS63308359A (ja) * 1987-06-10 1988-12-15 Mitsui Haitetsuku:Kk リ−ドフレ−ムの製造方法
JPS6414942A (en) * 1987-07-08 1989-01-19 Mitsubishi Electric Corp Resin sealed semiconductor integrated circuit device
JPS6481257A (en) * 1987-09-22 1989-03-27 Nitto Denko Corp Resin-sealed semiconductor device
JP2699517B2 (ja) * 1988-02-24 1998-01-19 モトローラ・インコーポレーテッド 丸形またはテーパ状エッジおよびコーナーを有する半導体デバイス
JPH01243531A (ja) * 1988-03-25 1989-09-28 Hitachi Ltd 半導体装置
JPH01251747A (ja) * 1988-03-31 1989-10-06 Toshiba Corp 半導体装置およびその製造方法
JPH022046A (ja) * 1988-06-10 1990-01-08 Nec Data Terminal Ltd 多目的シリアルプリンタ
JPH02138765A (ja) * 1988-07-28 1990-05-28 Seiko Epson Corp 半導体装置
JPH0290663A (ja) * 1988-09-28 1990-03-30 Hitachi Cable Ltd リードフレーム
JPH02129953A (ja) * 1988-11-09 1990-05-18 Seiko Epson Corp 半導体材料
JPH0383366A (ja) * 1989-08-28 1991-04-09 Matsushita Electron Corp 半導体装置
JPH03293756A (ja) * 1990-04-12 1991-12-25 Mitsubishi Electric Corp 半導体装置用リードフレーム及びその製造方法
US5196725A (en) * 1990-06-11 1993-03-23 Hitachi Cable Limited High pin count and multi-layer wiring lead frame

Also Published As

Publication number Publication date
US5440170A (en) 1995-08-08
DE69128464D1 (de) 1998-01-29
EP0503072A4 (en) 1993-10-06
EP0503072A1 (de) 1992-09-16
KR960003853B1 (ko) 1996-03-23
KR920702549A (ko) 1992-09-04
EP0503072B1 (de) 1997-12-17
WO1992004730A1 (en) 1992-03-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee