DE69127748D1 - Ein Halbleiterspeicher mit getrennter Steuerung von inaktiven Zeitspannen für Lese- und Schreibbetrieb - Google Patents

Ein Halbleiterspeicher mit getrennter Steuerung von inaktiven Zeitspannen für Lese- und Schreibbetrieb

Info

Publication number
DE69127748D1
DE69127748D1 DE69127748T DE69127748T DE69127748D1 DE 69127748 D1 DE69127748 D1 DE 69127748D1 DE 69127748 T DE69127748 T DE 69127748T DE 69127748 T DE69127748 T DE 69127748T DE 69127748 D1 DE69127748 D1 DE 69127748D1
Authority
DE
Germany
Prior art keywords
read
semiconductor memory
write operation
separate control
inactive periods
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69127748T
Other languages
English (en)
Other versions
DE69127748T2 (de
Inventor
Thomas Allyn Coker
David Charles Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69127748D1 publication Critical patent/DE69127748D1/de
Application granted granted Critical
Publication of DE69127748T2 publication Critical patent/DE69127748T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE69127748T 1990-12-14 1991-12-12 Ein Halbleiterspeicher mit getrennter Steuerung von inaktiven Zeitspannen für Lese- und Schreibbetrieb Expired - Fee Related DE69127748T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/627,236 US5258952A (en) 1990-12-14 1990-12-14 Semiconductor memory with separate time-out control for read and write operations

Publications (2)

Publication Number Publication Date
DE69127748D1 true DE69127748D1 (de) 1997-10-30
DE69127748T2 DE69127748T2 (de) 1998-03-12

Family

ID=24513802

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69127748T Expired - Fee Related DE69127748T2 (de) 1990-12-14 1991-12-12 Ein Halbleiterspeicher mit getrennter Steuerung von inaktiven Zeitspannen für Lese- und Schreibbetrieb

Country Status (5)

Country Link
US (1) US5258952A (de)
EP (1) EP0490679B1 (de)
JP (1) JP3609837B2 (de)
KR (1) KR100228620B1 (de)
DE (1) DE69127748T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574866A (en) * 1993-04-05 1996-11-12 Zenith Data Systems Corporation Method and apparatus for providing a data write signal with a programmable duration
GB9325301D0 (en) * 1993-12-10 1994-02-16 D2B Systems Co Ltd Local communication system and station for use in such a system
US5530677A (en) * 1994-08-31 1996-06-25 International Business Machines Corporation Semiconductor memory system having a write control circuit responsive to a system clock and/or a test clock for enabling and disabling a read/write latch
US5526322A (en) * 1994-09-23 1996-06-11 Xilinx, Inc. Low-power memory device with accelerated sense amplifiers
KR960019978A (ko) * 1994-11-23 1996-06-17 문정환 펄스 발생기
KR0136668B1 (ko) * 1995-02-16 1998-05-15 문정환 메모리의 펄스 발생회로
JP3102301B2 (ja) * 1995-05-24 2000-10-23 株式会社日立製作所 半導体記憶装置
US5657292A (en) * 1996-01-19 1997-08-12 Sgs-Thomson Microelectronics, Inc. Write pass through circuit
US5712584A (en) * 1996-01-19 1998-01-27 Sgs-Thomson Microelectronics, Inc. Synchronous stress test control
US5767709A (en) * 1996-01-19 1998-06-16 Sgs-Thomson Microelectronics, Inc. Synchronous test mode initalization
US5864696A (en) * 1996-01-19 1999-01-26 Stmicroelectronics, Inc. Circuit and method for setting the time duration of a write to a memory cell
US5801563A (en) * 1996-01-19 1998-09-01 Sgs-Thomson Microelectronics, Inc. Output driver circuitry having a single slew rate resistor
JPH09282886A (ja) * 1996-01-19 1997-10-31 Sgs Thomson Microelectron Inc メモリセルへの書込の開始をトラッキングする回路及び方法
JPH09231770A (ja) * 1996-01-19 1997-09-05 Sgs Thomson Microelectron Inc メモリセルへの書込を終了させる回路及び方法
US5619456A (en) * 1996-01-19 1997-04-08 Sgs-Thomson Microelectronics, Inc. Synchronous output circuit
US5701275A (en) * 1996-01-19 1997-12-23 Sgs-Thomson Microelectronics, Inc. Pipelined chip enable control circuitry and methodology
US6181640B1 (en) 1997-06-24 2001-01-30 Hyundai Electronics Industries Co., Ltd. Control circuit for semiconductor memory device
US6529993B1 (en) 2000-10-12 2003-03-04 International Business Machines Corp. Data and data strobe circuits and operating protocol for double data rate memories
JP4731730B2 (ja) * 2001-06-04 2011-07-27 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP2003196977A (ja) * 2001-12-27 2003-07-11 Fujitsu Ltd 半導体記憶装置のデータアクセス方法、及び半導体記憶装置
US6690606B2 (en) * 2002-03-19 2004-02-10 Micron Technology, Inc. Asynchronous interface circuit and method for a pseudo-static memory device
US20040059954A1 (en) * 2002-09-20 2004-03-25 Rainer Hoehler Automatic low power state entry
US6920524B2 (en) 2003-02-03 2005-07-19 Micron Technology, Inc. Detection circuit for mixed asynchronous and synchronous memory operation
JP4088227B2 (ja) * 2003-09-29 2008-05-21 株式会社東芝 半導体集積回路装置
JP2005108327A (ja) * 2003-09-30 2005-04-21 Toshiba Corp 半導体集積回路装置及びそのアクセス方法
JP2005117153A (ja) * 2003-10-03 2005-04-28 Toshiba Corp 無線通信装置、無線通信方法、及び無線通信媒体
US6914849B2 (en) * 2003-10-16 2005-07-05 International Business Machines Corporation Method and apparatus for reducing power consumption in a memory array with dynamic word line driver/decoders
US7560956B2 (en) * 2005-08-03 2009-07-14 Micron Technology, Inc. Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals
US7917719B2 (en) * 2006-12-04 2011-03-29 Sandisk Corporation Portable module interface with timeout prevention by dummy blocks
WO2008070053A2 (en) * 2006-12-04 2008-06-12 Sandisk Corporation Portable module interface with timeout prevention by dummy blocks
US7908501B2 (en) 2007-03-23 2011-03-15 Silicon Image, Inc. Progressive power control of a multi-port memory device
CN108319353B (zh) * 2018-04-23 2024-05-31 深圳市心流科技有限公司 电源使能电路

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4580246A (en) * 1983-11-02 1986-04-01 Motorola, Inc. Write protection circuit and method for a control register
JPH0766665B2 (ja) * 1988-03-31 1995-07-19 株式会社東芝 半導体記憶装置
US5031150A (en) * 1988-08-26 1991-07-09 Kabushiki Kaisha Toshiba Control circuit for a semiconductor memory device and semiconductor memory system
JPH07118196B2 (ja) * 1988-12-28 1995-12-18 株式会社東芝 スタティック型半導体メモリ
KR940008295B1 (ko) * 1989-08-28 1994-09-10 가부시기가이샤 히다찌세이사꾸쇼 반도체메모리
US5031141A (en) * 1990-04-06 1991-07-09 Intel Corporation Apparatus for generating self-timing for on-chip cache
US5128897A (en) * 1990-09-26 1992-07-07 Sgs-Thomson Microelectronics, Inc. Semiconductor memory having improved latched repeaters for memory row line selection
US5124951A (en) * 1990-09-26 1992-06-23 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with sequenced latched row line repeaters
US5124584A (en) * 1990-10-22 1992-06-23 Sgs-Thomson Microelectronics, Inc. Address buffer circuit with transition-based latching
US5126975A (en) * 1990-10-24 1992-06-30 Integrated Device Technology, Inc. Integrated cache SRAM memory having synchronous write and burst read

Also Published As

Publication number Publication date
EP0490679A2 (de) 1992-06-17
EP0490679B1 (de) 1997-09-24
US5258952A (en) 1993-11-02
JPH04301293A (ja) 1992-10-23
EP0490679A3 (en) 1992-10-14
DE69127748T2 (de) 1998-03-12
KR100228620B1 (ko) 1999-11-01
KR920013450A (ko) 1992-07-29
JP3609837B2 (ja) 2005-01-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee