DE69125982T2 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69125982T2
DE69125982T2 DE69125982T DE69125982T DE69125982T2 DE 69125982 T2 DE69125982 T2 DE 69125982T2 DE 69125982 T DE69125982 T DE 69125982T DE 69125982 T DE69125982 T DE 69125982T DE 69125982 T2 DE69125982 T2 DE 69125982T2
Authority
DE
Germany
Prior art keywords
lines
signal
response
switching circuit
bit line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69125982T
Other languages
English (en)
Other versions
DE69125982D1 (de
Inventor
Tadahiko Sugibayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69125982D1 publication Critical patent/DE69125982D1/de
Publication of DE69125982T2 publication Critical patent/DE69125982T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE69125982T 1990-07-17 1991-07-16 Halbleiterspeicheranordnung Expired - Lifetime DE69125982T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18853090 1990-07-17

Publications (2)

Publication Number Publication Date
DE69125982D1 DE69125982D1 (de) 1997-06-12
DE69125982T2 true DE69125982T2 (de) 1997-08-21

Family

ID=16225321

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69125982T Expired - Lifetime DE69125982T2 (de) 1990-07-17 1991-07-16 Halbleiterspeicheranordnung

Country Status (3)

Country Link
US (1) US5305265A (de)
EP (1) EP0467638B1 (de)
DE (1) DE69125982T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5848008A (en) * 1997-09-25 1998-12-08 Siemens Aktiengesellschaft Floating bitline test mode with digitally controllable bitline equalizers
JPH11328972A (ja) * 1998-05-18 1999-11-30 Mitsubishi Electric Corp 半導体装置、その設計方法およびその検査方法
JP2002109281A (ja) * 2000-09-28 2002-04-12 Toshiba Corp 半導体装置、半導体装置の販売方法、半導体装置の販売システム及び半導体装置の販売プログラムを記録した記録媒体
DE10344879B4 (de) * 2003-09-26 2005-11-24 Infineon Technologies Ag Integrierter Speicher und Verfahren zum Funktionstest des integrierten Speichers
WO2018151088A1 (ja) * 2017-02-14 2018-08-23 国立大学法人東北大学 メモリ装置
US10262732B2 (en) * 2017-08-03 2019-04-16 Winbond Electronics Corp. Programmable array logic circuit and operating method thereof
KR20190067669A (ko) * 2017-12-07 2019-06-17 에스케이하이닉스 주식회사 전자장치

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4687951A (en) * 1984-10-29 1987-08-18 Texas Instruments Incorporated Fuse link for varying chip operating parameters
US4656612A (en) * 1984-11-19 1987-04-07 Inmos Corporation Dram current control technique
US4748595A (en) * 1985-09-04 1988-05-31 Siemens Aktiengesellschaft Circuit arrangement comprising a matrix-shaped memory arrangement for variably adjustable delay of digital signals
JPH0812760B2 (ja) * 1986-11-29 1996-02-07 三菱電機株式会社 ダイナミックメモリ装置
JPH01194194A (ja) * 1988-01-29 1989-08-04 Nec Ic Microcomput Syst Ltd 半導体メモリ装置
US5051995A (en) * 1988-03-14 1991-09-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having a test mode setting circuit
JPH02206087A (ja) * 1989-02-03 1990-08-15 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
EP0467638B1 (de) 1997-05-07
US5305265A (en) 1994-04-19
EP0467638A3 (en) 1993-05-05
DE69125982D1 (de) 1997-06-12
EP0467638A2 (de) 1992-01-22

Similar Documents

Publication Publication Date Title
EP0293933B1 (de) Dynamische Speicherschaltung mit einem Abfühlschema
CN1734672B (zh) 用于存储器件的隔离控制电路和方法
GB2152777A (en) Semiconductor memory
KR900015154A (ko) 디-램형 집적 반도체 메모리와 그 시험방법
KR970067365A (ko) 반도체 기억장치
US5243574A (en) Shared sense amplifier type semiconductor memory device
KR870000708A (ko) 동작검사를 행하는 반도체 메모리 장치
ATE77894T1 (de) Cmos-stromdetektorverstaerker.
KR100602188B1 (ko) 비트라인 센스앰프 및 이를 구비하는 반도체 메모리 소자
EP0264929A2 (de) Halbleiterspeicheranordnung mit verbesserter Bitzeilenordnung
US5519712A (en) Current mode test circuit for SRAM
KR890004332A (ko) 반도체 기억장치
KR920022291A (ko) 프리챠지된 비트선을 갖는 멀티 포트 메모리 장치
US4831597A (en) Dynamic random access semiconductor memory wherein the RAS and CAS strobes respectively select the bit line and word line pairs
US5361233A (en) Semiconductor memory apparatus
KR910001744A (ko) 반도체 기억장치
DE69125982T2 (de) Halbleiterspeicheranordnung
JPS57100689A (en) Semiconductor storage device
KR870009392A (ko) 반도체 기억장치
KR940007888A (ko) 반도체 기억장치
US4380055A (en) Static RAM memory cell
KR920013440A (ko) 열 디코드에 의한 비트 라인 등화 기능을 구비한 반도체 메모리
US5371716A (en) Semiconductor memory device and operating method therefor
EP0350860B1 (de) Halbleiterspeicher mit verbesserten Abfühlverstärkern
KR930003140A (ko) 비트선의 한정된 전위진폭의 반도체 기억장치와 그의 동작방법

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP