EP0467638A2 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung Download PDF

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Publication number
EP0467638A2
EP0467638A2 EP91306430A EP91306430A EP0467638A2 EP 0467638 A2 EP0467638 A2 EP 0467638A2 EP 91306430 A EP91306430 A EP 91306430A EP 91306430 A EP91306430 A EP 91306430A EP 0467638 A2 EP0467638 A2 EP 0467638A2
Authority
EP
European Patent Office
Prior art keywords
signal
lines
bit line
semiconductor memory
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP91306430A
Other languages
English (en)
French (fr)
Other versions
EP0467638B1 (de
EP0467638A3 (en
Inventor
Tadahiko C/O Nec Corporation Sugibayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of EP0467638A2 publication Critical patent/EP0467638A2/de
Publication of EP0467638A3 publication Critical patent/EP0467638A3/en
Application granted granted Critical
Publication of EP0467638B1 publication Critical patent/EP0467638B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories

Definitions

  • the semiconductor memory device has a memory cell array which includes a plurality of memory cells that are provided in array form and a plurality of bit lines and word lines connected to each of the memory cells where the bit lines are arranged in pairs, sense amplifiers which are provided one for each of the bit line pairs for amplifying the potential difference between the bit lines of the pair in response to an activating signal, a delay circuit which gives to the activating signal to a delay that varies in response to a control signal from a switching circuit and generates a selection signal, and selection switch means which connects the predetermined bit line pair and the I/O lines in response to the selection signal.
  • a delay circuit 6 generates a selection signal YSW which is obtained by delaying the sense amplifier activating signal SE by a predetermined length of time in response to a control signal DS from a switching circuit 5. Namely, when the control signal DS is at a nonactive level, the delay circuit 6 generates a selection signal YSW which is delayed by a predetermined length of time (6 to 10 ns) from the sense amplifier activating signal SE. When the control signal DS is at the active level, the delay circuit 6 generates a selection signal YSW delayed further by a predetermined length of time (2 to 4 ns) than the selection signal YSW for the case when the selection signal DS is at the nonactive level.
  • the potential difference between the wirings La and Lb which is further amplified by the data amplifier 7 that is activated by the selection signal YSW is output to the input and output terminals (not shown) as a read data through a common data bus, thereby completing the read operation of one data.
  • the selection signal YSW goes to the active level and the column decoder 3 raises the level of one of the signals for the selection switch 4 to the active level, there arises a situation in which a bit line pair whose potential difference is not yet amplified sufficiently well is connected to the I/O lines. As a result, not only it takes a longer time for data reading but also there may arise a read error due to the reversal of the levels of the pair of bit lines depending upon circumstances.
  • the switching circuit 5 includes a pad PD connected to a node N, a resistor R1 with one end connected to the node N1 and the other end connected to a fuse F1, a fuse F1 connected between the resistor R1 and a power terminal Vcc, a resistor R2 with its one end connected to the node N1 and the other end connected to a fuse F2, a fuse F2 connected between the resistor R2 and a grounding terminal, and an inverter circuit INV1.
  • the output of the inverter circuit INV1 that is, the control signal DS is brought to the high level by connecting the pad PD to the grounding potential. Since the control signal DS is at the high level, the sense amplifier activating signal SE propagates along the route of the delay element D1, the delay element D2, the inverter circuit INV2, the NAND gate G1, the NAND gate G2, and the inverter circuit INV3, and becomes a selection signal YSW which is delayed by the time DT0 + DT1 (see Fig. 2).
  • a function test is carried out in the state where the control signal DS is at the low level by bringing the TEST signal to the low level. If a read error is discovered as a result, the function test is given for a second time in the state where the control signal DS is at the high level by bringing the TEST signal to the high level. If no error is generated when the control signal DS is at the high level, the fuse F11 is melted, and the control signal DS is fixed permanently to the high level. As described in the above, a pad for switching can be done away with in this switching circuit 5. In this case, an internal signal such as a low active write enable (WE) signal may be employed as the TEST signal.
  • WE low active write enable
  • the delay circuit 16 is equipped with three routes along which the sense amplifier activating signal SE can propagate. Namely, when both of the control signals DS1 and DS2 are at the low level, the sense amplifier activating signal SE propagates along the route of a delay element D1, a NAND gate G3, and an inverter circuit INV3. When the control signal DS1 is at the high level, the sense amplifier activating signal SE goes by way of the delay elements D1 and D2, an inverter circuit INV2, a NAND gate G1, the NAND gate G3, and the inverter circuit INV3.
  • control signals have been employed in the present embodiment, but a similar effect is obtainable by the present invention even if the control signals of three or more kinds are employed. In that case, one only needs to provide three or more switching circuits with construction similar to the construction of the switching circuit as shown in Fig. 3, and four or more routes for the propagation of the sense amplifier activating signal SE as the delay circuit.

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
EP91306430A 1990-07-17 1991-07-16 Halbleiterspeicheranordnung Expired - Lifetime EP0467638B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP18853090 1990-07-17
JP188530/90 1990-07-17

Publications (3)

Publication Number Publication Date
EP0467638A2 true EP0467638A2 (de) 1992-01-22
EP0467638A3 EP0467638A3 (en) 1993-05-05
EP0467638B1 EP0467638B1 (de) 1997-05-07

Family

ID=16225321

Family Applications (1)

Application Number Title Priority Date Filing Date
EP91306430A Expired - Lifetime EP0467638B1 (de) 1990-07-17 1991-07-16 Halbleiterspeicheranordnung

Country Status (3)

Country Link
US (1) US5305265A (de)
EP (1) EP0467638B1 (de)
DE (1) DE69125982T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0907185A2 (de) * 1997-09-25 1999-04-07 Siemens Aktiengesellschaft Schwebende Bitleitungen Prüfmodus mit digital steuerbaren Bitleitungen-Abgleichschaltungen

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11328972A (ja) * 1998-05-18 1999-11-30 Mitsubishi Electric Corp 半導体装置、その設計方法およびその検査方法
JP2002109281A (ja) * 2000-09-28 2002-04-12 Toshiba Corp 半導体装置、半導体装置の販売方法、半導体装置の販売システム及び半導体装置の販売プログラムを記録した記録媒体
DE10344879B4 (de) * 2003-09-26 2005-11-24 Infineon Technologies Ag Integrierter Speicher und Verfahren zum Funktionstest des integrierten Speichers
US10957371B2 (en) * 2017-02-14 2021-03-23 Tohoku University Memory device that enables direct block copying between cell configurations in different operation modes
US10262732B2 (en) * 2017-08-03 2019-04-16 Winbond Electronics Corp. Programmable array logic circuit and operating method thereof
KR20190067669A (ko) * 2017-12-07 2019-06-17 에스케이하이닉스 주식회사 전자장치
CN118398040A (zh) * 2023-01-17 2024-07-26 长鑫存储技术有限公司 一种存储电路及存储器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4687951A (en) * 1984-10-29 1987-08-18 Texas Instruments Incorporated Fuse link for varying chip operating parameters
JPS63138597A (ja) * 1986-11-29 1988-06-10 Mitsubishi Electric Corp ダイナミツクメモリ装置
EP0326183A2 (de) * 1988-01-29 1989-08-02 Nec Corporation Pseudo-statischer Direktzugriffspeicher

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656612A (en) * 1984-11-19 1987-04-07 Inmos Corporation Dram current control technique
US4748595A (en) * 1985-09-04 1988-05-31 Siemens Aktiengesellschaft Circuit arrangement comprising a matrix-shaped memory arrangement for variably adjustable delay of digital signals
US5051995A (en) * 1988-03-14 1991-09-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having a test mode setting circuit
JPH02206087A (ja) * 1989-02-03 1990-08-15 Mitsubishi Electric Corp 半導体記憶装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4687951A (en) * 1984-10-29 1987-08-18 Texas Instruments Incorporated Fuse link for varying chip operating parameters
JPS63138597A (ja) * 1986-11-29 1988-06-10 Mitsubishi Electric Corp ダイナミツクメモリ装置
EP0326183A2 (de) * 1988-01-29 1989-08-02 Nec Corporation Pseudo-statischer Direktzugriffspeicher

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN. vol. 27, no. 6, November 1984, NEW YORK US pages 3604 - 3605 GRAY 'Automatic delay increase/decrease testing for FET memories' *
PATENT ABSTRACTS OF JAPAN vol. 012, no. 399 (P-775)24 October 1988 & JP-A-63 138 597 ( MITSUBISHI ) 10 June 1988 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0907185A2 (de) * 1997-09-25 1999-04-07 Siemens Aktiengesellschaft Schwebende Bitleitungen Prüfmodus mit digital steuerbaren Bitleitungen-Abgleichschaltungen
EP0907185A3 (de) * 1997-09-25 1999-09-15 Siemens Aktiengesellschaft Schwebende Bitleitungen Prüfmodus mit digital steuerbaren Bitleitungen-Abgleichschaltungen

Also Published As

Publication number Publication date
DE69125982T2 (de) 1997-08-21
EP0467638B1 (de) 1997-05-07
EP0467638A3 (en) 1993-05-05
US5305265A (en) 1994-04-19
DE69125982D1 (de) 1997-06-12

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