DE69125588T2 - Verfahren zur Herstellung von Substraten mit dielektrischer Trennung - Google Patents

Verfahren zur Herstellung von Substraten mit dielektrischer Trennung

Info

Publication number
DE69125588T2
DE69125588T2 DE69125588T DE69125588T DE69125588T2 DE 69125588 T2 DE69125588 T2 DE 69125588T2 DE 69125588 T DE69125588 T DE 69125588T DE 69125588 T DE69125588 T DE 69125588T DE 69125588 T2 DE69125588 T2 DE 69125588T2
Authority
DE
Germany
Prior art keywords
substrates
production
dielectric separation
dielectric
separation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69125588T
Other languages
English (en)
Other versions
DE69125588D1 (de
Inventor
Yutaka Ohta
Konomu Ohki
Masatake Katayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of DE69125588D1 publication Critical patent/DE69125588D1/de
Application granted granted Critical
Publication of DE69125588T2 publication Critical patent/DE69125588T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE69125588T 1990-12-28 1991-12-24 Verfahren zur Herstellung von Substraten mit dielektrischer Trennung Expired - Fee Related DE69125588T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2417208A JPH07118505B2 (ja) 1990-12-28 1990-12-28 誘電体分離基板の製造方法

Publications (2)

Publication Number Publication Date
DE69125588D1 DE69125588D1 (de) 1997-05-15
DE69125588T2 true DE69125588T2 (de) 1997-11-27

Family

ID=18525333

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69125588T Expired - Fee Related DE69125588T2 (de) 1990-12-28 1991-12-24 Verfahren zur Herstellung von Substraten mit dielektrischer Trennung

Country Status (4)

Country Link
US (1) US5183783A (de)
EP (1) EP0493116B1 (de)
JP (1) JPH07118505B2 (de)
DE (1) DE69125588T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0817166B2 (ja) * 1991-04-27 1996-02-21 信越半導体株式会社 超薄膜ｓｏｉ基板の製造方法及び製造装置
JP3175188B2 (ja) * 1991-05-10 2001-06-11 ソニー株式会社 位置合わせマークの形成方法
DE69332407T2 (de) * 1992-06-17 2003-06-18 Harris Corp Herstellung von Halbleiteranordnungen auf SOI substraten
KR100275712B1 (ko) * 1992-10-12 2000-12-15 윤종용 반도체 소자의 게이트 산화막 형성방법
JP3301170B2 (ja) * 1993-08-09 2002-07-15 ソニー株式会社 半導体装置の製法
JP3033655B2 (ja) * 1993-09-28 2000-04-17 日本電気株式会社 半導体装置及び半導体装置の製造方法
US5449638A (en) * 1994-06-06 1995-09-12 United Microelectronics Corporation Process on thickness control for silicon-on-insulator technology
US6815774B1 (en) 1998-10-29 2004-11-09 Mitsubishi Materials Silicon Corporation Dielectrically separated wafer and method of the same
US6500694B1 (en) 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6984571B1 (en) * 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6563133B1 (en) * 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
US6524881B1 (en) * 2000-08-25 2003-02-25 Micron Technology, Inc. Method and apparatus for marking a bare semiconductor die
JP2002141253A (ja) * 2000-10-31 2002-05-17 Disco Abrasive Syst Ltd 半導体装置
US7169685B2 (en) * 2002-02-25 2007-01-30 Micron Technology, Inc. Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
US7317278B2 (en) * 2003-01-31 2008-01-08 Cabot Microelectronics Corporation Method of operating and process for fabricating an electron source
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
CN105712286B (zh) * 2014-12-02 2018-03-30 中芯国际集成电路制造(上海)有限公司 Mems器件的制作方法
CN113161229A (zh) * 2021-04-12 2021-07-23 上海新昇半导体科技有限公司 多晶硅薄膜衬底的制备方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3385729A (en) * 1964-10-26 1968-05-28 North American Rockwell Composite dual dielectric for isolation in integrated circuits and method of making
US3624467A (en) * 1969-02-17 1971-11-30 Texas Instruments Inc Monolithic integrated-circuit structure and method of fabrication
JPS5329551B2 (de) * 1974-08-19 1978-08-22
JPS58122747A (ja) * 1982-01-14 1983-07-21 Fujitsu Ltd 半導体装置の製造方法
KR850004178A (ko) * 1983-11-30 1985-07-01 야마모도 다꾸마 유전체 분리형 집적회로 장치의 제조방법
US4631804A (en) * 1984-12-10 1986-12-30 At&T Bell Laboratories Technique for reducing substrate warpage springback using a polysilicon subsurface strained layer
US4649630A (en) * 1985-04-01 1987-03-17 Motorola, Inc. Process for dielectrically isolated semiconductor structure
US4606936A (en) * 1985-04-12 1986-08-19 Harris Corporation Stress free dielectric isolation technology
JPH0355822A (ja) * 1989-07-25 1991-03-11 Shin Etsu Handotai Co Ltd 半導体素子形成用基板の製造方法

Also Published As

Publication number Publication date
JPH07118505B2 (ja) 1995-12-18
DE69125588D1 (de) 1997-05-15
JPH04251957A (ja) 1992-09-08
EP0493116A2 (de) 1992-07-01
US5183783A (en) 1993-02-02
EP0493116A3 (en) 1994-06-15
EP0493116B1 (de) 1997-04-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee