DE69119463D1 - Kontaktierung und deren Herstellungsverfahren für Halbleiterbauelemente - Google Patents

Kontaktierung und deren Herstellungsverfahren für Halbleiterbauelemente

Info

Publication number
DE69119463D1
DE69119463D1 DE69119463T DE69119463T DE69119463D1 DE 69119463 D1 DE69119463 D1 DE 69119463D1 DE 69119463 T DE69119463 T DE 69119463T DE 69119463 T DE69119463 T DE 69119463T DE 69119463 D1 DE69119463 D1 DE 69119463D1
Authority
DE
Germany
Prior art keywords
contacting
semiconductor devices
manufacturing processes
processes
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69119463T
Other languages
English (en)
Other versions
DE69119463T2 (de
Inventor
Vida Ilderem
Alan G Solheim
Rick C Jerome
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Application granted granted Critical
Publication of DE69119463D1 publication Critical patent/DE69119463D1/de
Publication of DE69119463T2 publication Critical patent/DE69119463T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69119463T 1990-04-02 1991-03-16 Kontaktierung und deren Herstellungsverfahren für Halbleiterbauelemente Expired - Lifetime DE69119463T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/503,336 US5107321A (en) 1990-04-02 1990-04-02 Interconnect method for semiconductor devices

Publications (2)

Publication Number Publication Date
DE69119463D1 true DE69119463D1 (de) 1996-06-20
DE69119463T2 DE69119463T2 (de) 1997-01-02

Family

ID=24001664

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69119463T Expired - Lifetime DE69119463T2 (de) 1990-04-02 1991-03-16 Kontaktierung und deren Herstellungsverfahren für Halbleiterbauelemente

Country Status (5)

Country Link
US (1) US5107321A (de)
EP (1) EP0450375B1 (de)
JP (1) JPH04226064A (de)
KR (1) KR100199465B1 (de)
DE (1) DE69119463T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5410173A (en) * 1991-01-28 1995-04-25 Kikushima; Ken'ichi Semiconductor integrated circuit device
US5629547A (en) * 1991-04-23 1997-05-13 Intel Corporation BICMOS process for counter doped collector
GB2255226B (en) * 1991-04-23 1995-03-01 Intel Corp Bicmos process for counter doped collector
JPH05226589A (ja) * 1992-02-17 1993-09-03 Mitsubishi Electric Corp Ｃ−ＢｉＣＭＯＳ型半導体装置およびその製造方法
US5286991A (en) * 1992-08-26 1994-02-15 Pioneer Semiconductor Corporation Capacitor for a BiCMOS device
JPH0685177A (ja) * 1992-08-31 1994-03-25 Hitachi Ltd 半導体集積回路装置
EP0595484A1 (de) * 1992-10-22 1994-05-04 National Semiconductor Corporation NMOS LDD PMOS HALO IC Herstellungsverfahren für CMOS Transistoren
JP2886420B2 (ja) * 1992-10-23 1999-04-26 三菱電機株式会社 半導体装置の製造方法
JP3462886B2 (ja) * 1993-03-11 2003-11-05 株式会社東芝 半導体装置
US5506158A (en) * 1994-07-27 1996-04-09 Texas Instruments Incorporated BiCMOS process with surface channel PMOS transistor
US5824577A (en) * 1995-02-16 1998-10-20 National Semiconductor Corporation MOSFET with reduced leakage current
US5478762A (en) * 1995-03-16 1995-12-26 Taiwan Semiconductor Manufacturing Company Method for producing patterning alignment marks in oxide
US6911681B1 (en) 2004-04-14 2005-06-28 International Business Machines Corporation Method of base formation in a BiCMOS process
US20090042395A1 (en) * 2007-07-13 2009-02-12 Chien-Ling Chan Spacer process for CMOS fabrication with bipolar transistor leakage prevention
US8274110B2 (en) 2009-05-20 2012-09-25 Micron Technology, Inc. Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
US8421164B2 (en) 2010-01-05 2013-04-16 Micron Technology, Inc. Memory cell array with semiconductor selection device for multiple memory cells
US8969154B2 (en) 2011-08-23 2015-03-03 Micron Technology, Inc. Methods for fabricating semiconductor device structures and arrays of vertical transistor devices
US20170373174A1 (en) * 2016-06-25 2017-12-28 Texas Instruments Incorporated Radiation enhanced bipolar transistor

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3955269A (en) * 1975-06-19 1976-05-11 International Business Machines Corporation Fabricating high performance integrated bipolar and complementary field effect transistors
US4374700A (en) * 1981-05-29 1983-02-22 Texas Instruments Incorporated Method of manufacturing silicide contacts for CMOS devices
US4507847A (en) * 1982-06-22 1985-04-02 Ncr Corporation Method of making CMOS by twin-tub process integrated with a vertical bipolar transistor
JPS58225663A (ja) * 1982-06-23 1983-12-27 Toshiba Corp 半導体装置の製造方法
US4558507A (en) * 1982-11-12 1985-12-17 Nec Corporation Method of manufacturing semiconductor device
US4536945A (en) * 1983-11-02 1985-08-27 National Semiconductor Corporation Process for producing CMOS structures with Schottky bipolar transistors
JPS60134466A (ja) * 1983-12-23 1985-07-17 Hitachi Ltd 半導体装置およびその製造方法
JPS6116571A (ja) * 1984-07-03 1986-01-24 Ricoh Co Ltd 半導体装置の製造方法
US4609568A (en) * 1984-07-27 1986-09-02 Fairchild Camera & Instrument Corporation Self-aligned metal silicide process for integrated circuits having self-aligned polycrystalline silicon electrodes
CA1258320A (en) * 1985-04-01 1989-08-08 Madhukar B. Vora Small contactless ram cell
US4764480A (en) * 1985-04-01 1988-08-16 National Semiconductor Corporation Process for making high performance CMOS and bipolar integrated devices on one substrate with reduced cell size
EP0197531B1 (de) * 1985-04-08 1993-07-28 Hitachi, Ltd. Dünnfilmtransistor auf isolierendem Substrat
US4648175A (en) * 1985-06-12 1987-03-10 Ncr Corporation Use of selectively deposited tungsten for contact formation and shunting metallization
US4929992A (en) * 1985-09-18 1990-05-29 Advanced Micro Devices, Inc. MOS transistor construction with self aligned silicided contacts to gate, source, and drain regions
KR910002831B1 (ko) * 1986-04-23 1991-05-06 아메리칸 텔리폰 앤드 텔레그라프 캄파니 반도체 소자 제조공정
JPS63114261A (ja) * 1986-09-11 1988-05-19 フェアチャイルド　セミコンダクタ　コーポレーション トランジスタ用の自己整合型ベース分路
WO1989011733A1 (en) * 1988-05-24 1989-11-30 Micron Technology, Inc. Alpha shielded tisi2 local interconnects
US4877755A (en) * 1988-05-31 1989-10-31 Texas Instruments Incorporated Method of forming silicides having different thicknesses

Also Published As

Publication number Publication date
US5107321A (en) 1992-04-21
EP0450375A1 (de) 1991-10-09
JPH04226064A (ja) 1992-08-14
KR910019142A (ko) 1991-11-30
DE69119463T2 (de) 1997-01-02
EP0450375B1 (de) 1996-05-15
KR100199465B1 (ko) 1999-06-15

Similar Documents

Publication Publication Date Title
DE69131762D1 (de) Herstellungsverfahren für Halbleitereinrichtungen
DE69430511T2 (de) Halbleiteranordnung und Herstellungverfahren
DE69119463D1 (de) Kontaktierung und deren Herstellungsverfahren für Halbleiterbauelemente
DE69133497D1 (de) Leiterrahmen für eine Halbleiteranordnung und dessen Herstellungsverfahren
DE69534636D1 (de) Halbleitervorrichtung und deren Herstellungsverfahren
DE69522514T2 (de) Halbleiteranordnung und Herstellungsverfahren
DE69526539D1 (de) Halbleiteranordnung und Herstellungsverfahren
DE69527330D1 (de) Halbleiteranordnung und Herstellungsverfahren
DE69124646D1 (de) MOS-Halbleiterbauelement und dessen Herstellungsverfahren
DE69331052T2 (de) Integrierte Randstruktur für Hochspannung-Halbleiteranordnungen und dazugehöriger Herstellungsprozess
DE69522195D1 (de) Herstellungsverfahren für Halbleiteranordnungen
DE69232611T2 (de) Gestapelte Chip-Anordnung und Herstellungsverfahren für dieselbe
DE69207285D1 (de) Isoliertes Trägerelement für Halbleitervorrichtung und Verfahren zu deren Herstellung
DE69323127D1 (de) Halbleitervorrichtung und Herstellungsverfahren
DE69413602T2 (de) Halbleiteranordnung und Herstellungsverfahren
DE69429906T2 (de) Halbleiterstruktur und Herstellungsverfahren
DE69424728T2 (de) Halbleiteranordnung und zugehörige Herstellungsmethode
DE69325343D1 (de) Halbleiteranordnung und Herstellungsverfahren dafür
DE69315125D1 (de) Herstellungsverfahren für Halbleiterbauelement mit Kondensator
DE69131241T2 (de) Herstellungsverfahren für Halbleiteranordnungen
DE69509959T2 (de) Halbleitervorrichtungen sowie deren Herstellungsverfahren
DE68925219D1 (de) Halbleiterlaser-Vorrichtung und Herstellungsverfahren für die Halbleiterlaser-Vorrichtung
DE3855551D1 (de) Halbleiter-Laservorrichtung und deren Herstellungsverfahren
DE69015458D1 (de) Elektrodenstruktur für III-V-Verbindungshalbleiterbauelement und deren Herstellungsverfahren.
DE69034109D1 (de) Halbleiter-IC-Vorrichtung und deren Herstellungsverfahren

Legal Events

Date Code Title Description
8364 No opposition during term of opposition