DE69112486D1 - Halbleiteranordnung mit ventilierenden isolierenden Schichten. - Google Patents

Halbleiteranordnung mit ventilierenden isolierenden Schichten.

Info

Publication number
DE69112486D1
DE69112486D1 DE69112486T DE69112486T DE69112486D1 DE 69112486 D1 DE69112486 D1 DE 69112486D1 DE 69112486 T DE69112486 T DE 69112486T DE 69112486 T DE69112486 T DE 69112486T DE 69112486 D1 DE69112486 D1 DE 69112486D1
Authority
DE
Germany
Prior art keywords
insulating layers
semiconductor arrangement
ventilating
ventilating insulating
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69112486T
Other languages
English (en)
Other versions
DE69112486T2 (de
Inventor
Hideki Gomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69112486D1 publication Critical patent/DE69112486D1/de
Publication of DE69112486T2 publication Critical patent/DE69112486T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69112486T 1990-05-08 1991-05-08 Halbleiteranordnung mit ventilierenden isolierenden Schichten. Expired - Fee Related DE69112486T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11816490 1990-05-08

Publications (2)

Publication Number Publication Date
DE69112486D1 true DE69112486D1 (de) 1995-10-05
DE69112486T2 DE69112486T2 (de) 1996-04-11

Family

ID=14729695

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69112486T Expired - Fee Related DE69112486T2 (de) 1990-05-08 1991-05-08 Halbleiteranordnung mit ventilierenden isolierenden Schichten.

Country Status (4)

Country Link
US (1) US5189502A (de)
EP (1) EP0456240B1 (de)
KR (1) KR940005723B1 (de)
DE (1) DE69112486T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508228A (en) * 1994-02-14 1996-04-16 Microelectronics And Computer Technology Corporation Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same
JPH0964037A (ja) * 1995-08-23 1997-03-07 Mitsubishi Electric Corp 半導体装置の製造方法
US5843831A (en) * 1997-01-13 1998-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Process independent alignment system
JP3019021B2 (ja) * 1997-03-31 2000-03-13 日本電気株式会社 半導体装置及びその製造方法
US6153936A (en) * 1997-11-07 2000-11-28 Winbond Electronics, Corp. Method for forming via hole and semiconductor structure formed thereby
US6822256B2 (en) * 2001-09-18 2004-11-23 Intel Corporation Forming organic light emitting device displays
JP4232044B2 (ja) * 2005-07-05 2009-03-04 セイコーエプソン株式会社 半導体装置の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0245290A1 (de) * 1985-11-04 1987-11-19 Motorola, Inc. Dielektrikum aus intermetallischem glas
WO1988007762A1 (en) * 1987-03-30 1988-10-06 Eastman Kodak Company Two-level metal interconnection
JPH01138734A (ja) * 1987-11-25 1989-05-31 Mitsubishi Electric Corp 複導電体層を有する半導体装置およびその製造方法

Also Published As

Publication number Publication date
US5189502A (en) 1993-02-23
EP0456240A2 (de) 1991-11-13
DE69112486T2 (de) 1996-04-11
EP0456240A3 (en) 1992-04-29
KR940005723B1 (ko) 1994-06-23
EP0456240B1 (de) 1995-08-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee