WO1988007762A1

WO1988007762A1 - Two-level metal interconnection

Info

Publication number: WO1988007762A1
Application number: PCT/US1988/000857
Authority: WO
Inventors: Howard Edgar Rhodes
Original assignee: Eastman Kodak Company
Priority date: 1987-03-30
Filing date: 1988-03-21
Publication date: 1988-10-06

Abstract

A two-level metallization system is used in a two-phase CCD for connection to the first-phase (14) and second-phase (16) set of electrodes. The two-level system includes two layers of aluminum (18, 20) spaced apart by a composite dielectric (19) which comprises an inner and an outer layer of silicon oxide deposited by low-temperature chemical-vapor-deposition and an intermediate layer of spun-on glass.

Description

TWO LEVEL METAL INTERCONNECTION Technical Field

This invention relates to the manufacture of silicon integrated circuit devices and more particu- larly to such devices which include two levels of metallization for interconnection to the electrodes of the devices. Background Art

As integrated circuits become more complex, there is an increasing.need for the use of two levels of metal to interconnect the various circuit elements into the desired circuit. When two levels of metallization are used there is need for electrical isolation between the two levels and so the need to interpose a layer of a suitable dielectric between the two metal layers.

This dielectric advantageously should have the following properties. It should have good planarization properties to compensate for the surface irregularities that may be present in the lower layer of metal by the need for such layer to fill via holes to contact the electrodes of the circuit elements. It should show good isolation properties with high breakdown characteristics in relatively thin films. Additionally, it should not require processing at high temperatures since such processing might undesirably result in migration or movement of the dopants previously introduced into the silicon substrate to provide the desired electrical parameters to the circuit, and if aluminum has been used, undesirably result in oxidation of the aluminum.

Various forms of dielectric layers have been used to provide the desired isolation but none is entirely satisfactory. Disclosure of the Invention

The present invention relates an improvement in a two—level metallization system achieved by the use as interlevel isolation a layer of spun—on glass between two layers of low—temperature chemical— vapor-deposited silicon oxide.

In one aspect this invention is directed to an integrated circuit device which includes a semiconductive substrate including a plurality of electrodes on the substrate and a pair of substan¬ tially planar and. parallel metal layers for providing connections to the electrodes characterized in that the metal layers are electrically isolated from one another by a composite dielectric including a first layer of silicon oxide, a second layer of spun—on glass superimposed on the first layer, and a third layer of silicon_oxide superimposed over the second layer. Brief Description of the Drawing The invention will be discussed in more detail hereinafter taken in conjunction with the accompanying drawing in which:

FIG. 1 shows in cross—section a two phase charge—coupled device (CCD) which includes an interconnection system involving two levels of metallization in accordance with the invention; and

FIG. 2 is a section taken along the lines 2—2 of FIG. 1 showing in more detail the two level metallization system. It should be appreciated that the drawing is not to scale for ease of exposition. Modes of Carrying Out the Invention

FIG. 1 shows a longitudinal section taken along the signal channel axis of a two—phase CCD which may be conventional except for the novel two—level metallization system. It comprises a silicon substrate 10 provided with a silicon oxide layer 12 over its upper surface. A two—phase gate electrode system compris¬ ing the first-phase gate electrodes 14 (of which only two are shown) and the second-phase gate electrodes 16 (of which only one is shown) overlies the gate oxide layer 12 in the usual fashion. To step the signal charge packets between successive potential wells defined by the electrodes 14 and 16, a source of electric voltage needs to be connected between the electrode set 14 and electrode set 16. It is usual to include.1-ocalized fixed charges, provided by extra doping in the substrate underlying one edge region of each gate electrode, to cooperate with the electric field provided by the gate electrodes to insure the desired directionality of charge trans¬ fer. Additionally it is usual to include fixed charges along the upper surface of the substrate to form a buried channel for transport of the signal charges to minimize surface effects. Since use of such charges is well known, they have not been shown in the drawing in the interest of simplicity. This invention has particular usefulness incorporated in such a device. To provide the operating voltages to the electrode system, it is necessary to provide an electrical connection to each of the electrodes. To this end, there is provided a first level of metallization comprising the substantially planar aluminum layer 18 for connection to each of first- phase gate electrodes 14 and a second level of metallization comprising the substantially planar aluminum layer 20 for connection to each of the second—phase gate electrodes 16. The layers 18, 20 are separated by dielectric material 19. Although in the drawing, the layer 18 is discontinuous in the plane of the section shown, in fact it would be continuous in other sections. It is these voids in layer 18, necessitated by the need to permit access by the second level of metal 20 to the second phase gate electrodes 16, that impose special requirements on the interlevel dielectric 19 so that good planarization may be obtained for the second level of metal. As seen in more detail in FIG. 2, the dielectric 19 in accordance with the invention is a composite layer including substantially planar layers 19A and 19C which are of silicon oxide and substan¬ tially planar layer 19B, intermediate between layers 19A and 19C, which is of spun—on glass, for example, a commercial glass, trademarked Accuglass—105, a product of Allied Chemical, which is amenable to easy deposit and ready flow for use in a spun—on process without undue heating, for example, above about 500 degrees Centigrade.

In this composite layer, the two oxide layers serve primarily to provide the dielectric isolation and voltage breakdown protection while the spun—on glass layer serves primarily to provide the topographical smoothing and planarization of the composite layer, so that the two oxide layers may be substantially planar and parallel.

In one embodiment tested, each aluminum layer 18, 20 was deposited by bias sputtering in known fashion to a thickness of about 8000

Angstroms. Moreover, the first or lower oxide layer 19A was deposited undoped by low—temperature chemical—vapor—deposition to an average thickness of 2000 Angstroms in known fashion and the second or upper oxide layer 19C was also deposited undoped by low—temperature chemical—vapor—deposition to an average thickness of about 4000 Angstroms. The intermediate layer 19B of spun glass had an average thickness of about 1500 Angstroms and was annealed a about 450 degrees Centigrade in pure nitrogen for about thirty (30) minutes after being spun on.

In practice, before the deposition of the first aluminum layer it is advantageous to provide a dielectric layer non—selectively over both the first and second—phase set of gate electrodes. This may advantageously be a layer of boro—phospho—silicate glass deposited by low pressure chemical vapor deposition for planarization at a temperature of 900 degrees Centigrade to form a layer having a thickness of about 5000 Angstroms. It is usually desirable to preface its deposit with a deposit of a layer of silicon oxide deposited undoped by low temperatures CVD to an average thickness of about 1000 Angstroms. Moreover, before the non—selective deposit of the first level of aluminum, it is necessary to form contact holes appropriately in the previously deposited dielectric to expose portions of the first—phase set of gate electrodes. To this end, it is usually advantageous to employ reactive—ion—etch¬ ing in known fashion to form contact openings with substantially vertical side walls to facilitate close packing.

Moreover, before deposit of the interlevel dielectric 19, the first level of aluminum metalliza¬ tion 18 is patterned in known fashion. After non—selective deposition of the interlevel dielectric 19 and before deposition of the second aluminum layer 20, it is necessary to provide contact holes in the interlevel dielectric to expose portions of the second—phase set of gate electrodes so electrical connections can be provided thereto. This similarly can be done in known fashion using reactive—ion-etching to form holes with substantially vertical side walls. Industrial Applicability and Advantages

It should be understood that the specific embodiment described is merely illustrative of one embodiment of the invention and various modifications may be made in this embodiment consistent with the scope of the invention. For example, the specific dimensions and particular materials mentioned represent one design and other designs are feasible. Similarly, while the invention has been described, for use in improving a two—phase CCD, it can be used in other forms of integrated circuit devices where two levels of metallization are needed. It should be feasible to use the invention in metallization systems employing more than two levels of metal, for example three.

Claims

What is Claimed is:

1. An integrated circuit device which includes a se iconductive substrate including a plurality of electrodes on the substrate and a pair of substantially planar and parallel metal layers for providing connections to the electrodes characterized in that the metal layers are electrically isolated from one another by a composite dielectric including a first layer of silicon oxide, a second layer of spun—on glass superimposed on the first layer, and a third layer of silicon oxide superimposed over the second layer.

2. The integrated circuit device of claim 1 in which each of the pair of metal layers is of aluminum.

3. The integrated circuit device of claim 1 in which the first and third layers of the composite dielectric are of silicon oxide deposited by low—temperature chemical—vapor—deposition.

4. The integrated circuit device of claim

3 in which the first layer is about 2000 Angstroms thick, the second layer is about 1500 Angstroms thick, and the third layer is about 4000 Angstroms thick.

5. The integrated circuit device of claim

4 in which each of the pair of metal layers is of aluminum and about 8000 Angstroms thick.

6. The integrated circuit device of claim 1 in which between the electrodes and the first of the pair of metal layers there are included a layer of silicon oxide and a layer of borophosphosilicate glass.

7. The process of forming an isolation dielectric between two metal layers comprising the steps of depositing by low—temperature chemical— vapor-deposition a first layer of silicon oxide over the first of the metal layers, spinning over the layer of silicon oxide a glass layer of the kind which can be annealed at temperatures below about 500°C, and depositing by low—temperature chemical— vapor-deposition a second layer of silicon oxide over the spun glass layer, and depositing the second layer of metal over the second layer of silicon oxide.