DE69105753D1 - Herstellungsmethode einer dünnschichtmehrlagenstruktur. - Google Patents

Herstellungsmethode einer dünnschichtmehrlagenstruktur.

Info

Publication number
DE69105753D1
DE69105753D1 DE69105753T DE69105753T DE69105753D1 DE 69105753 D1 DE69105753 D1 DE 69105753D1 DE 69105753 T DE69105753 T DE 69105753T DE 69105753 T DE69105753 T DE 69105753T DE 69105753 D1 DE69105753 D1 DE 69105753D1
Authority
DE
Germany
Prior art keywords
thin
manufacturing
layer
layer structure
multiple layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69105753T
Other languages
English (en)
Other versions
DE69105753T2 (de
Inventor
Kenneth Chang
George Czornyj
Mukta Farooq
Ananda Kumar
Marvin Pittler
Heinz Steimel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69105753D1 publication Critical patent/DE69105753D1/de
Application granted granted Critical
Publication of DE69105753T2 publication Critical patent/DE69105753T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/467—Adding a circuit layer by thin film methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1031—Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/072—Electroless plating, e.g. finish plating or initial plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69105753T 1990-11-15 1991-02-01 Herstellungsmethode einer dünnschichtmehrlagenstruktur. Expired - Fee Related DE69105753T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US61319690A 1990-11-15 1990-11-15
PCT/US1991/000703 WO1992009102A1 (en) 1990-11-15 1991-02-01 A method of making a multilayer thin film structure

Publications (2)

Publication Number Publication Date
DE69105753D1 true DE69105753D1 (de) 1995-01-19
DE69105753T2 DE69105753T2 (de) 1995-05-24

Family

ID=24456274

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69105753T Expired - Fee Related DE69105753T2 (de) 1990-11-15 1991-02-01 Herstellungsmethode einer dünnschichtmehrlagenstruktur.

Country Status (4)

Country Link
EP (1) EP0557278B1 (de)
JP (1) JPH0746755B2 (de)
DE (1) DE69105753T2 (de)
WO (1) WO1992009102A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2649533B1 (fr) * 1989-07-04 1991-09-20 Thomson Tubes Electroniques Tube a grille a sortie sur cavites couplees, avec element de couplage integre au tube
EP0609496B1 (de) * 1993-01-19 1998-04-15 Siemens Aktiengesellschaft Verfahren zur Herstellung einer Kontakte und diese verbindende Leiterbahnen umfassenden Metallisierungsebene
JP3234757B2 (ja) * 1995-12-05 2001-12-04 インターナショナル・ビジネス・マシーンズ・コーポレーション 多層配線基板及びその製造方法
US5837427A (en) * 1996-04-30 1998-11-17 Samsung Electro-Mechanics Co Co., Ltd. Method for manufacturing build-up multi-layer printed circuit board
FR2785761B1 (fr) * 1998-11-05 2002-01-25 Rapide Circuit Imprime Rci Procede pour realiser des connexions electriques
JP4558413B2 (ja) * 2004-08-25 2010-10-06 新光電気工業株式会社 基板、半導体装置、基板の製造方法、及び半導体装置の製造方法
KR101288163B1 (ko) * 2011-10-25 2013-07-18 삼성전기주식회사 무수축 세라믹 기판 및 이의 제조 방법
JP6169955B2 (ja) * 2013-04-17 2017-07-26 新光電気工業株式会社 配線基板及びその製造方法
JP6247032B2 (ja) * 2013-07-01 2017-12-13 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1379558A (en) * 1971-05-15 1975-01-02 Int Computers Ltd Methods of manufacture of multilayer circuit structures
JPS515568A (en) * 1974-07-05 1976-01-17 Oki Electric Ind Co Ltd Tasohaisenkairono seizohoho
JPS56138993A (en) * 1980-04-01 1981-10-29 Nippon Telegraph & Telephone Method of producing multilayer printed cirucit board
JPS60180197A (ja) * 1984-02-27 1985-09-13 宇部興産株式会社 多層プリント配線板の製造方法
US4705606A (en) * 1985-01-31 1987-11-10 Gould Inc. Thin-film electrical connections for integrated circuits
EP0211180A3 (de) * 1985-08-02 1989-08-09 Shipley Company Inc. Herstellungsverfahren für mehrschichtige Leiterplatten
JPS6251294A (ja) * 1985-08-30 1987-03-05 株式会社日立製作所 多層配線板の製造方法
US4789648A (en) * 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
JPH0693123B2 (ja) * 1986-06-12 1994-11-16 日本電信電話株式会社 感光性高分子膜およびこれを用いた多層配線板
IT1191680B (it) * 1986-03-19 1988-03-23 Gte Telecom Spa Processo per la realizzazione di fori metallizzati in un substrato dotato di cammini conduttivi e resistivi,e prodotto ottenuto con il processo suddetto
JPS62291095A (ja) * 1986-06-10 1987-12-17 日立化成工業株式会社 配線板の製造方法
JPS62295493A (ja) * 1986-06-14 1987-12-22 工業技術院長 高速素子実装用回路基板の製造方法
JPS6314494A (ja) * 1986-07-07 1988-01-21 日本電気株式会社 多層回路基板
JPS6318697A (ja) * 1986-07-11 1988-01-26 日本電気株式会社 多層配線基板
JPS6386550A (ja) * 1986-09-30 1988-04-16 Pioneer Electronic Corp 多層配線層の形成方法
JPS63155691A (ja) * 1986-12-18 1988-06-28 株式会社東芝 多層配線回路基板
US4774127A (en) * 1987-06-15 1988-09-27 Tektronix, Inc. Fabrication of a multilayer conductive pattern on a dielectric substrate
JPH0298994A (ja) * 1988-10-06 1990-04-11 Ibiden Co Ltd ポリイミド絶縁層上への導体層形成方法
DE3840207A1 (de) * 1988-11-29 1990-05-31 Draegerwerk Ag Verfahren zur herstellung einer leiterplatte mit mehreren leiterbahnebenen und entsprechende multilayer-leiterplatte
DE3907004A1 (de) * 1989-03-04 1990-09-06 Contraves Ag Verfahren zum herstellen von duennschichtschaltungen
JPH02254788A (ja) * 1989-03-28 1990-10-15 Nec Corp 多層印刷配線基板
US5108553A (en) * 1989-04-04 1992-04-28 Olin Corporation G-tab manufacturing process and the product produced thereby

Also Published As

Publication number Publication date
EP0557278A1 (de) 1993-09-01
WO1992009102A1 (en) 1992-05-29
JPH05509198A (ja) 1993-12-16
JPH0746755B2 (ja) 1995-05-17
DE69105753T2 (de) 1995-05-24
EP0557278B1 (de) 1994-12-07

Similar Documents

Publication Publication Date Title
DE3575903D1 (de) Befestigung mit einer zeitweiligen verbindungsschicht.
DE3583422D1 (de) Mehrschichtleitersubstrat.
FI841899A0 (fi) Bestrykningsanordning.
DE68923957D1 (de) Herstellungsverfahren einer gleitvorrichtung.
ES545443A0 (es) Un metodo de revestir un substrato con una pluralidad de capas de polimero.
ES547591A0 (es) Un metodo de revestir un substrato con capas multiples de polimero.
DE69114355D1 (de) Modifizierung einer Polyimidoberfläche.
FI862046A (fi) Haerdbara kompositioner som innehaoller en polyepoxid och en halogenerad tvaobasisk fenol samt av dessa framstaellda impregnerade substrat och laminat.
ES554538A0 (es) Un metodo de fabricar una estructura fotovoltaica.
DE69008974D1 (de) Elektroabscheidung einer Palladiumschicht.
DE3784537D1 (de) Herstellungsverfahren einer niedergeschlagenen schicht.
NO862695L (no) Ekspanderbart fibersjiktfilter.
DE69105753T2 (de) Herstellungsmethode einer dünnschichtmehrlagenstruktur.
FI854288A0 (fi) Bestrykningsanordning.
ES550422A0 (es) Metodo para fabricar un sustrato revestido.
DE69623177D1 (de) Bauelement mit einer Schicht aus beta-C3N4
BR8903430A (pt) Estrutura de multiplas camadas
DE68921253T2 (de) Verfahren zur Abscheidung einer dünnen Supraleiterschicht.
DE3783632D1 (de) Herstellungsverfahren einer niedergeschlagenen schicht.
NO861975L (no) Overflatebelegningsprosess.
DE69315975T2 (de) Herstellungsverfahren einer keramischen komponente
DE3850920T2 (de) Zusammengesetzte supraleitende Schichtstruktur.
DE68908226T2 (de) Zeitweilig rostbeständige Überzugsmasse.
DE3575044D1 (de) Fotoleitende schicht.
DE69219979D1 (de) Herstellungsverfahren einer Isolationschicht

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee