DE69102770D1 - Hochgeschwindigkeitstester und Verfahren zur Erzeugung aufeinanderfolgender Schleifen von Datensignalen einer bestimmten Taktrate. - Google Patents
Hochgeschwindigkeitstester und Verfahren zur Erzeugung aufeinanderfolgender Schleifen von Datensignalen einer bestimmten Taktrate.Info
- Publication number
- DE69102770D1 DE69102770D1 DE69102770T DE69102770T DE69102770D1 DE 69102770 D1 DE69102770 D1 DE 69102770D1 DE 69102770 T DE69102770 T DE 69102770T DE 69102770 T DE69102770 T DE 69102770T DE 69102770 D1 DE69102770 D1 DE 69102770D1
- Authority
- DE
- Germany
- Prior art keywords
- data
- high speed
- test
- cache
- data signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31919—Storing and outputting test patterns
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/602,433 US5195097A (en) | 1990-10-19 | 1990-10-19 | High speed tester |
PCT/US1991/001364 WO1992007322A1 (en) | 1990-10-19 | 1991-02-27 | High speed tester |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69102770D1 true DE69102770D1 (de) | 1994-08-11 |
DE69102770T2 DE69102770T2 (de) | 1995-01-05 |
Family
ID=24411337
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69102770T Expired - Fee Related DE69102770T2 (de) | 1990-10-19 | 1991-02-27 | Hochgeschwindigkeitstester und Verfahren zur Erzeugung aufeinanderfolgender Schleifen von Datensignalen einer bestimmten Taktrate. |
Country Status (5)
Country | Link |
---|---|
US (1) | US5195097A (de) |
EP (1) | EP0553080B1 (de) |
JP (1) | JPH07122855B2 (de) |
DE (1) | DE69102770T2 (de) |
WO (1) | WO1992007322A1 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5260946A (en) * | 1991-06-03 | 1993-11-09 | Hughes Missile Systems Company | Self-testing and self-configuration in an integrated circuit |
US5805794A (en) * | 1996-03-28 | 1998-09-08 | Cypress Semiconductor Corp. | CPLD serial programming with extra read register |
US5768288A (en) * | 1996-03-28 | 1998-06-16 | Cypress Semiconductor Corp. | Method and apparatus for programming a programmable logic device having verify logic for comparing verify data read from a memory location with program data |
US5815510A (en) * | 1996-03-28 | 1998-09-29 | Cypress Semiconductor Corp. | Serial programming of instruction codes in different numbers of clock cycles |
US5835503A (en) * | 1996-03-28 | 1998-11-10 | Cypress Semiconductor Corp. | Method and apparatus for serially programming a programmable logic device |
JP3833341B2 (ja) * | 1997-05-29 | 2006-10-11 | 株式会社アドバンテスト | Ic試験装置のテストパターン発生回路 |
US6859901B2 (en) * | 2000-12-27 | 2005-02-22 | Winbond Electronics Corp. | Method for testing memories with seamless data input/output by interleaving seamless bank commands |
ITRM20030354A1 (it) * | 2003-07-17 | 2005-01-18 | Micron Technology Inc | Unita' di controllo per dispositivo di memoria. |
US8103924B2 (en) * | 2008-01-29 | 2012-01-24 | Globalfoundries Inc. | Test access mechanism for multi-core processor or other integrated circuit |
US9559987B1 (en) * | 2008-09-26 | 2017-01-31 | Tellabs Operations, Inc | Method and apparatus for improving CAM learn throughput using a cache |
US9262292B2 (en) * | 2012-06-11 | 2016-02-16 | New York University | Test access system, method and computer-accessible medium for chips with spare identical cores |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3806888A (en) * | 1972-12-04 | 1974-04-23 | Ibm | Hierarchial memory system |
US4323968A (en) * | 1978-10-26 | 1982-04-06 | International Business Machines Corporation | Multilevel storage system having unitary control of data transfers |
DE3023699A1 (de) * | 1980-06-25 | 1982-01-14 | Ibm Deutschland Gmbh, 7000 Stuttgart | Verfahren und anordnung zur erzeugung von impulsen vorgegebener zeitrelation innerhalb vorgegebener impulsintervalle mit hoher zeitlicher aufloesung |
US4451918A (en) * | 1981-10-09 | 1984-05-29 | Teradyne, Inc. | Test signal reloader |
JPS5990067A (ja) * | 1982-11-15 | 1984-05-24 | Advantest Corp | 論理回路試験用パタ−ン発生装置 |
US4598245B1 (en) * | 1983-06-13 | 1993-11-16 | Circuit tester having indirect counters | |
US4696005A (en) * | 1985-06-03 | 1987-09-22 | International Business Machines Corporation | Apparatus for reducing test data storage requirements for high speed VLSI circuit testing |
US4682330A (en) * | 1985-10-11 | 1987-07-21 | International Business Machines Corporation | Hierarchical test system architecture |
US4796222A (en) * | 1985-10-28 | 1989-01-03 | International Business Machines Corporation | Memory structure for nonsequential storage of block bytes in multi-bit chips |
US4931723A (en) * | 1985-12-18 | 1990-06-05 | Schlumberger Technologies, Inc. | Automatic test system having a "true tester-per-pin" architecture |
US4994732A (en) * | 1985-12-18 | 1991-02-19 | Schlumberger Technologies, Inc. | Automatic test system having a "true tester-per-pin" architecture |
DE3613896A1 (de) * | 1986-04-24 | 1987-10-29 | Siemens Ag | Einrichtung und verfahren fuer die ein- oder ausgabe binaerer daten, insbesondere testdaten digitaler prueflinge |
US4730318A (en) * | 1986-11-24 | 1988-03-08 | International Business Machines Corporation | Modular organized storage tester |
-
1990
- 1990-10-19 US US07/602,433 patent/US5195097A/en not_active Expired - Fee Related
-
1991
- 1991-02-27 EP EP91907664A patent/EP0553080B1/de not_active Expired - Lifetime
- 1991-02-27 DE DE69102770T patent/DE69102770T2/de not_active Expired - Fee Related
- 1991-02-27 WO PCT/US1991/001364 patent/WO1992007322A1/en active IP Right Grant
- 1991-02-27 JP JP3507151A patent/JPH07122855B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0553080A1 (de) | 1993-08-04 |
EP0553080B1 (de) | 1994-07-06 |
JPH07122855B2 (ja) | 1995-12-25 |
DE69102770T2 (de) | 1995-01-05 |
JPH05507163A (ja) | 1993-10-14 |
US5195097A (en) | 1993-03-16 |
WO1992007322A1 (en) | 1992-04-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |