KR840006851A - 데이타 자동연속 처리회로 - Google Patents

데이타 자동연속 처리회로 Download PDF

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Publication number
KR840006851A
KR840006851A KR1019830005368A KR830005368A KR840006851A KR 840006851 A KR840006851 A KR 840006851A KR 1019830005368 A KR1019830005368 A KR 1019830005368A KR 830005368 A KR830005368 A KR 830005368A KR 840006851 A KR840006851 A KR 840006851A
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KR
South Korea
Prior art keywords
data
memory
pulse
data processing
address
Prior art date
Application number
KR1019830005368A
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English (en)
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KR870001112B1 (ko
Inventor
시게노리 도꾸미쓰
Original Assignee
사바 쇼오이찌
도오쿄오 시바우덴기 가부시기 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 사바 쇼오이찌, 도오쿄오 시바우덴기 가부시기 가이샤 filed Critical 사바 쇼오이찌
Publication of KR840006851A publication Critical patent/KR840006851A/ko
Application granted granted Critical
Publication of KR870001112B1 publication Critical patent/KR870001112B1/ko

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22Microcontrol or microprogram arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T9/00Image coding
    • G06T9/005Statistical coding, e.g. Huffman, run length coding
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/46Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00Television systems
    • H04N7/025Systems for the transmission of digital non-picture data, e.g. of text during the active part of a television frame
    • H04N7/035Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Television Signal Processing For Recording (AREA)
  • Memory System (AREA)
  • Prepayment Telephone Systems (AREA)
  • Meter Arrangements (AREA)
  • Selective Calling Equipment (AREA)
  • Television Systems (AREA)
  • Digital Computer Display Output (AREA)

Abstract

내용없음

Description

데이타 자동연속 처리회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 회로가 사용되는 개소를 설명하는데 표시한 개략도.
제2도는 본 발명의 한 실시예를 표시하는 구성 설명도.
제3도는 제2도의 회로에서 사용되는 신호의 파형도.

Claims (1)

  1. 메모리에 대한 어드레스 데이타를 격납하기 위한 어드레스 레지스터겸 카운터수단과, 상기 어드레스 데이타를 인크리멘트 펄스가 입력된 때에 수정하고 상기 메모리에 대한 어드레스 지정위치를 변경하기 위한 인크리멘트 수단과, 상기 메모리에의 써넣기 데이타 또는 상기 메모리에서의 읽어내기 데이타를 격납하기 위한 데이타 레지스터 수단과, 상기 메모리에의 데이타 써넣기회수 또는 상기 메모리에서의 데이타 읽어내기 회수에 대응한 계수치가 셋트되어, 이 계수치에 비슷한 수의 클럭펄스가 입력하였을 때에 그 검출신호를 얻는 데이타 처리회수 검출수단과, 상기 데이타 처리회수 검출수단과, 상기 데이타 레지스터 수단에 마이크로 컴퓨터에서의 데이타가 셋트된 것을 검지하고 제1의 액세스기간의 시발펄스가 입력하는 것에 의해서, 상기 검출신호가 존재하지 않는 것을 조건으로 위해 상기 어드레스 레지스터 겸 카운터수단의 어드레스 데이타를 상기 메모리에 부여하기 위한 펄스발생부 상기 데이타 처리회수 검출수단에 상기 클럭펄스를 부여하기 위한 회로부, 상기 데이타 레지스터 수단의 데이타 게이트회로를 도통시키기 위해 펄스를 출력하는 회로부를 보유함과 동시에 상기 제1의 액세스기간의 종료펄스가 입력하는 것에 의해서, 상기 인크리멘트 펄스를 출력하기 위한 회로부를 가진 액세스 제어회로를 구비한 것을 특징으로 하는 데이타 자동연속 처리회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019830005368A 1982-11-11 1983-11-11 데이타 자동연속 처리회로 KR870001112B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP198206 1982-11-11
JP57198206A JPS5987569A (ja) 1982-11-11 1982-11-11 デ−タ自動連続処理回路
JP57-198206 1982-11-11

Publications (2)

Publication Number Publication Date
KR840006851A true KR840006851A (ko) 1984-12-03
KR870001112B1 KR870001112B1 (ko) 1987-06-08

Family

ID=16387241

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830005368A KR870001112B1 (ko) 1982-11-11 1983-11-11 데이타 자동연속 처리회로

Country Status (5)

Country Link
US (1) US4845662A (ko)
JP (1) JPS5987569A (ko)
KR (1) KR870001112B1 (ko)
DE (1) DE3340919A1 (ko)
GB (1) GB2129984B (ko)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS617175U (ja) * 1984-06-20 1986-01-17 三洋電機株式会社 画像表示装置
JPS63243989A (ja) * 1987-03-31 1988-10-11 株式会社東芝 メモリ制御装置
US5210851A (en) * 1988-01-08 1993-05-11 Hewlett-Packard Company High capacity tape drive transparently writes and reads large packets of blocked data between interblock gaps
GB9020596D0 (en) * 1990-09-21 1990-10-31 Alcatel Business Systems Data transmission method and apparatus
US5584044A (en) * 1990-09-28 1996-12-10 Fuji Photo Film Co., Ltd. Integrated circuit memory card for write in/read out capability having plurality of latching means for expandable addressing using counting means for enabling latches thereof
US5206935A (en) * 1991-03-26 1993-04-27 Sinks Rod G Apparatus and method for fast i/o data transfer in an intelligent cell
US5367674A (en) * 1991-12-13 1994-11-22 International Business Machines Corporation Data stream optimizer utilizing difference coding between a current state buffer and a next state buffer
US5404172A (en) * 1992-03-02 1995-04-04 Eeg Enterprises, Inc. Video signal data and composite synchronization extraction circuit for on-screen display
WO1994014284A1 (en) * 1992-12-09 1994-06-23 Discovery Communications, Inc. Reprogrammable terminal for suggesting programs offered on a television program delivery system
US7168084B1 (en) 1992-12-09 2007-01-23 Sedna Patent Services, Llc Method and apparatus for targeting virtual objects
US9286294B2 (en) 1992-12-09 2016-03-15 Comcast Ip Holdings I, Llc Video and digital multimedia aggregator content suggestion engine
US5684542A (en) * 1993-12-21 1997-11-04 Sony Corporation Video subtitle processing system
DE4423232A1 (de) * 1994-07-02 1996-01-04 Thomson Brandt Gmbh Verfahren zur Minimierung des Speicheraufwandes für Teletextdaten
US5677739A (en) * 1995-03-02 1997-10-14 National Captioning Institute System and method for providing described television services
US5548338A (en) * 1995-06-07 1996-08-20 News American Publishing, Inc. Compression of an electronic programming guide
US6031577A (en) * 1997-07-10 2000-02-29 Thomson Consumer Electronics, Inc. System for forming and processing program specific information containing text data for terrestrial, cable or satellite broadcast
US7793326B2 (en) 2001-08-03 2010-09-07 Comcast Ip Holdings I, Llc Video and digital multimedia aggregator
US7908628B2 (en) 2001-08-03 2011-03-15 Comcast Ip Holdings I, Llc Video and digital multimedia aggregator content coding and formatting
GB0123410D0 (en) * 2001-09-28 2001-11-21 Memquest Ltd Memory system for data storage and retrieval
US6680738B1 (en) 2002-02-22 2004-01-20 Neomagic Corp. Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3789367A (en) * 1972-06-29 1974-01-29 Ibm Memory access device
US4043933A (en) * 1976-06-15 1977-08-23 United Technologies Corporation Method of fabricating a fuel cell electrode
US4054951A (en) * 1976-06-30 1977-10-18 International Business Machines Corporation Data expansion apparatus
GB1585100A (en) * 1976-09-06 1981-02-25 Gen Electric Co Ltd Electronic display apparatus
FR2382049A1 (fr) * 1977-02-23 1978-09-22 Thomson Csf Processeur pour terminal informatique utilisant un recepteur de television
NL7704398A (nl) * 1977-04-22 1978-10-24 Philips Nv Inrichting voor het afbeelden van gegevens op een weergeeftoestel.
US4394774A (en) * 1978-12-15 1983-07-19 Compression Labs, Inc. Digital video compression system and methods utilizing scene adaptive coding with rate buffer feedback
US4414645A (en) * 1979-04-30 1983-11-08 Honeywell Information Systems Inc. Hardware-firmware CRT display link system
JPS6031423B2 (ja) * 1979-08-17 1985-07-22 富士通株式会社 圧縮デ−タ復元方式
US4249172A (en) * 1979-09-04 1981-02-03 Honeywell Information Systems Inc. Row address linking control system for video display terminal
US4449145A (en) * 1980-01-24 1984-05-15 Zenith Radio Corporation Intelligent teletext decoder
US4412252A (en) * 1981-06-01 1983-10-25 Ncr Corporation Image reduction system
JPS58129876A (ja) * 1981-12-29 1983-08-03 Fujitsu Ltd フアクシミリ装置

Also Published As

Publication number Publication date
US4845662A (en) 1989-07-04
DE3340919C2 (ko) 1988-04-07
DE3340919A1 (de) 1984-05-17
KR870001112B1 (ko) 1987-06-08
JPS5987569A (ja) 1984-05-21
GB2129984A (en) 1984-05-23
GB8329770D0 (en) 1983-12-14
GB2129984B (en) 1986-07-02

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