DE69025520D1 - Speicher mit verbessertem Bitzeilenausgleich - Google Patents

Speicher mit verbessertem Bitzeilenausgleich

Info

Publication number
DE69025520D1
DE69025520D1 DE69025520T DE69025520T DE69025520D1 DE 69025520 D1 DE69025520 D1 DE 69025520D1 DE 69025520 T DE69025520 T DE 69025520T DE 69025520 T DE69025520 T DE 69025520T DE 69025520 D1 DE69025520 D1 DE 69025520D1
Authority
DE
Germany
Prior art keywords
memory
bit line
line compensation
improved bit
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69025520T
Other languages
English (en)
Other versions
DE69025520T2 (de
Inventor
Mark D Bader
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE69025520D1 publication Critical patent/DE69025520D1/de
Application granted granted Critical
Publication of DE69025520T2 publication Critical patent/DE69025520T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE69025520T 1989-09-05 1990-08-31 Speicher mit verbessertem Bitzeilenausgleich Expired - Fee Related DE69025520T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/402,733 US5043945A (en) 1989-09-05 1989-09-05 Memory with improved bit line and write data line equalization

Publications (2)

Publication Number Publication Date
DE69025520D1 true DE69025520D1 (de) 1996-04-04
DE69025520T2 DE69025520T2 (de) 1996-08-29

Family

ID=23593101

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69025520T Expired - Fee Related DE69025520T2 (de) 1989-09-05 1990-08-31 Speicher mit verbessertem Bitzeilenausgleich

Country Status (6)

Country Link
US (1) US5043945A (de)
EP (1) EP0416827B1 (de)
JP (1) JP3131987B2 (de)
KR (1) KR960012049B1 (de)
DE (1) DE69025520T2 (de)
HK (1) HK1003808A1 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0810728B2 (ja) * 1990-02-01 1996-01-31 株式会社東芝 半導体記憶装置
US5398206A (en) * 1990-03-02 1995-03-14 Hitachi, Ltd. Semiconductor memory device with data error compensation
JP2892757B2 (ja) * 1990-03-23 1999-05-17 三菱電機株式会社 半導体集積回路装置
US5229967A (en) * 1990-09-04 1993-07-20 Nogle Scott G BICMOS sense circuit for sensing data during a read cycle of a memory
US5475635A (en) * 1990-10-01 1995-12-12 Motorola, Inc. Memory with a combined global data line load and multiplexer
KR940001644B1 (ko) * 1991-05-24 1994-02-28 삼성전자 주식회사 메모리 장치의 입출력 라인 프리차아지 방법
US5228106A (en) * 1991-05-30 1993-07-13 Integrated Device Technology, Inc. Track-and-regenerate amplifiers and memories using such amplifiers
WO1992022070A1 (en) * 1991-05-30 1992-12-10 Integrated Device Technology, Inc. Static memories and methods of reading static memories
KR940008296B1 (ko) * 1991-06-19 1994-09-10 삼성전자 주식회사 고속 센싱동작을 수행하는 센스앰프
FR2694826B1 (fr) * 1992-08-13 1994-09-16 Thomson Composants Militaires Circuit intégré de mémoire avec protection contre des perturbations.
JP2894115B2 (ja) * 1992-11-10 1999-05-24 松下電器産業株式会社 カラム選択回路
US6105152A (en) 1993-04-13 2000-08-15 Micron Technology, Inc. Devices and methods for testing cell margin of memory devices
US5416744A (en) * 1994-03-08 1995-05-16 Motorola Inc. Memory having bit line load with automatic bit line precharge and equalization
KR0127216B1 (ko) * 1994-11-24 1998-04-02 문정환 반도체 메모리장치
US5663908A (en) * 1995-07-06 1997-09-02 Micron Quantum Devices, Inc. Data input/output circuit for performing high speed memory data read operation
DE19632780A1 (de) * 1996-08-15 1998-02-19 Ibm Verbesserter Restore für Speicherzellen mittels negativer Bitline-Selektion
US5777935A (en) * 1997-03-12 1998-07-07 Motorola, Inc. Memory device with fast write recovery and related write recovery method
US6205058B1 (en) 1997-04-04 2001-03-20 Micron Technology, Inc. Data input/output circuit for performing high speed memory data read operation
US5828612A (en) * 1997-10-27 1998-10-27 Motorola, Inc. Method and circuit for controlling a precharge cycle of a memory device
US6590237B2 (en) * 1997-12-26 2003-07-08 Samsung Electronics Co., Ltd. Layout structure for dynamic random access memory
US6341099B1 (en) * 2000-09-29 2002-01-22 Intel Corporation Reducing power consumption in a data storage device
JP4088954B2 (ja) * 2002-03-04 2008-05-21 日本電気株式会社 半導体記憶装置の読み出し回路
JP4090967B2 (ja) * 2003-08-29 2008-05-28 松下電器産業株式会社 半導体記憶装置
US7218564B2 (en) * 2004-07-16 2007-05-15 Promos Technologies Inc. Dual equalization devices for long data line pairs
US9053776B2 (en) * 2012-11-08 2015-06-09 SK Hynix Inc. Setting information storage circuit and integrated circuit chip including the same

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4110840A (en) * 1976-12-22 1978-08-29 Motorola Inc. Sense line charging system for random access memory
JPS595989B2 (ja) * 1980-02-16 1984-02-08 富士通株式会社 スタティック型ランダムアクセスメモリ
US4355377A (en) * 1980-06-30 1982-10-19 Inmos Corporation Asynchronously equillibrated and pre-charged static ram
JPS5812193A (ja) * 1981-07-15 1983-01-24 Toshiba Corp 半導体メモリ
US4712194A (en) * 1984-06-08 1987-12-08 Matsushita Electric Industrial Co., Ltd. Static random access memory
JPS6132296A (ja) * 1984-07-23 1986-02-14 Oki Electric Ind Co Ltd 半導体メモリ装置
US4636991A (en) * 1985-08-16 1987-01-13 Motorola, Inc. Summation of address transition signals
US4712197A (en) * 1986-01-28 1987-12-08 Motorola, Inc. High speed equalization in a memory
US4751680A (en) * 1986-03-03 1988-06-14 Motorola, Inc. Bit line equalization in a memory
JPS63166090A (ja) * 1986-12-26 1988-07-09 Toshiba Corp スタティック型メモリ
JPS63211190A (ja) * 1987-02-26 1988-09-02 Nec Corp メモリ回路用内部クロツク信号発生器
JP2569538B2 (ja) * 1987-03-17 1997-01-08 ソニー株式会社 メモリ装置
JP2572607B2 (ja) * 1987-09-25 1997-01-16 セイコーエプソン株式会社 半導体記憶装置
US4802129A (en) * 1987-12-03 1989-01-31 Motorola, Inc. RAM with dual precharge circuit and write recovery circuitry
EP0320556B1 (de) * 1987-12-15 1991-02-27 International Business Machines Corporation Referenz-Spannungsgenerator für CMOS-Speicher
US4899317A (en) * 1988-02-01 1990-02-06 Motorola, Inc. Bit line precharge in a bimos ram
US4926383A (en) * 1988-02-02 1990-05-15 National Semiconductor Corporation BiCMOS write-recovery circuit

Also Published As

Publication number Publication date
KR910006992A (ko) 1991-04-30
EP0416827A2 (de) 1991-03-13
EP0416827A3 (en) 1993-04-28
US5043945A (en) 1991-08-27
HK1003808A1 (en) 1998-11-06
DE69025520T2 (de) 1996-08-29
JP3131987B2 (ja) 2001-02-05
KR960012049B1 (ko) 1996-09-11
JPH03100992A (ja) 1991-04-25
EP0416827B1 (de) 1996-02-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee