DE69022832T2 - Verfahren zur Bildung einer Germanium-Schicht und durch diese Schicht hergestellter Heteroübergangs-Bipolartransistor. - Google Patents

Verfahren zur Bildung einer Germanium-Schicht und durch diese Schicht hergestellter Heteroübergangs-Bipolartransistor.

Info

Publication number
DE69022832T2
DE69022832T2 DE69022832T DE69022832T DE69022832T2 DE 69022832 T2 DE69022832 T2 DE 69022832T2 DE 69022832 T DE69022832 T DE 69022832T DE 69022832 T DE69022832 T DE 69022832T DE 69022832 T2 DE69022832 T2 DE 69022832T2
Authority
DE
Germany
Prior art keywords
layer
forming
bipolar transistor
heterojunction bipolar
transistor made
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69022832T
Other languages
English (en)
Other versions
DE69022832D1 (de
Inventor
Douglas P Verret
Kenneth E Bean
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69022832D1 publication Critical patent/DE69022832D1/de
Publication of DE69022832T2 publication Critical patent/DE69022832T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66242—Heterojunction transistors [HBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/011—Bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/059—Germanium on silicon or Ge-Si on III-V

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
DE69022832T 1989-12-27 1990-12-18 Verfahren zur Bildung einer Germanium-Schicht und durch diese Schicht hergestellter Heteroübergangs-Bipolartransistor. Expired - Fee Related DE69022832T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/457,673 US5089428A (en) 1989-12-27 1989-12-27 Method for forming a germanium layer and a heterojunction bipolar transistor

Publications (2)

Publication Number Publication Date
DE69022832D1 DE69022832D1 (de) 1995-11-09
DE69022832T2 true DE69022832T2 (de) 1996-03-21

Family

ID=23817687

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69022832T Expired - Fee Related DE69022832T2 (de) 1989-12-27 1990-12-18 Verfahren zur Bildung einer Germanium-Schicht und durch diese Schicht hergestellter Heteroübergangs-Bipolartransistor.

Country Status (3)

Country Link
US (1) US5089428A (de)
EP (1) EP0435135B1 (de)
DE (1) DE69022832T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5162246A (en) * 1990-04-27 1992-11-10 North Carolina State University Selective germanium deposition on silicon and resulting structures
US5362657A (en) * 1992-11-25 1994-11-08 Texas Instruments Incorporated Lateral complementary heterojunction bipolar transistor and processing procedure
US5285089A (en) * 1992-12-02 1994-02-08 Kobe Steel U.S.A., Inc. Diamond and silicon carbide heterojunction bipolar transistor
US5354700A (en) * 1993-07-26 1994-10-11 United Microelectronics Corporation Method of manufacturing super channel TFT structure
US5422502A (en) * 1993-12-09 1995-06-06 Northern Telecom Limited Lateral bipolar transistor
US5466949A (en) * 1994-08-04 1995-11-14 Texas Instruments Incorporated Silicon oxide germanium resonant tunneling
US5516724A (en) * 1994-11-30 1996-05-14 Cornell Research Foundation, Inc. Oxidizing methods for making low resistance source/drain germanium contacts
US6723621B1 (en) * 1997-06-30 2004-04-20 International Business Machines Corporation Abrupt delta-like doping in Si and SiGe films by UHV-CVD
US6635110B1 (en) * 1999-06-25 2003-10-21 Massachusetts Institute Of Technology Cyclic thermal anneal for dislocation reduction
US6515287B2 (en) 2000-06-15 2003-02-04 Kla-Tencor Technologies Corporation Sectored magnetic lens and method of use
US6891167B2 (en) * 2000-06-15 2005-05-10 Kla-Tencor Technologies Apparatus and method for applying feedback control to a magnetic lens
DE10324065A1 (de) * 2003-05-27 2004-12-30 Texas Instruments Deutschland Gmbh Verfahren zur Herstellung eines integrierten Silizium-Germanium-Heterobipolartranistors und ein integrierter Silizium-Germanium Heterobipolartransitor
KR101216580B1 (ko) * 2004-03-10 2012-12-31 에이저 시스템즈 엘엘시 실리콘－게르마늄층에서 고 게르마늄 농도를 갖는 바이폴라 접합 트랜지스터 및 바이폴라 접합 트랜지스터를 형성하는 방법
US8227319B2 (en) 2004-03-10 2012-07-24 Agere Systems Inc. Bipolar junction transistor having a high germanium concentration in a silicon-germanium layer and a method for forming the bipolar junction transistor
FR2868202B1 (fr) * 2004-03-25 2006-05-26 Commissariat Energie Atomique Procede de preparation d'une couche de dioxyde de silicium par oxydation a haute temperature sur un substrat presentant au moins en surface du germanium ou un alliage sicicium- germanium.
KR100610465B1 (ko) * 2005-03-25 2006-08-08 주식회사 하이닉스반도체 반도체 소자의 제조 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3725161A (en) * 1971-03-03 1973-04-03 A Kuper Oxidation of semiconductive alloys and products obtained thereby
JPH0654775B2 (ja) * 1984-08-31 1994-07-20 日本電信電話株式会社 半導体装置の製造方法
JPS6218719A (ja) * 1985-07-17 1987-01-27 Fujitsu Ltd 半導体装置の製造方法
JPS6243163A (ja) * 1985-08-21 1987-02-25 Toshiba Corp 固体撮像装置
JPS62136036A (ja) * 1985-12-10 1987-06-19 Nec Corp 絶縁膜形成法
JPS62165975A (ja) * 1986-01-17 1987-07-22 Nec Corp ヘテロ構造バイポ−ラ・トランジスタ
US4920076A (en) * 1988-04-15 1990-04-24 The United States Of America As Represented By The United States Department Of Energy Method for enhancing growth of SiO2 in Si by the implantation of germanium
US4891329A (en) * 1988-11-29 1990-01-02 University Of North Carolina Method of forming a nonsilicon semiconductor on insulator structure
EP0380077A3 (de) * 1989-01-25 1990-09-12 Hitachi, Ltd. Transistor, versehen mit einer gedehnten Schicht aus Germanium
US4975387A (en) * 1989-12-15 1990-12-04 The United States Of America As Represented By The Secretary Of The Navy Formation of epitaxial si-ge heterostructures by solid phase epitaxy

Also Published As

Publication number Publication date
EP0435135B1 (de) 1995-10-04
US5089428A (en) 1992-02-18
DE69022832D1 (de) 1995-11-09
EP0435135A1 (de) 1991-07-03

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Legal Events

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8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: RAYTHEON CO., LEXINGTON, MASS., US

8339 Ceased/non-payment of the annual fee