DE69012520T2 - Halbleiterheterostruktur und Verfahren zu ihrer Herstellung. - Google Patents

Halbleiterheterostruktur und Verfahren zu ihrer Herstellung.

Info

Publication number
DE69012520T2
DE69012520T2 DE69012520T DE69012520T DE69012520T2 DE 69012520 T2 DE69012520 T2 DE 69012520T2 DE 69012520 T DE69012520 T DE 69012520T DE 69012520 T DE69012520 T DE 69012520T DE 69012520 T2 DE69012520 T2 DE 69012520T2
Authority
DE
Germany
Prior art keywords
manufacture
semiconductor heterostructure
heterostructure
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69012520T
Other languages
English (en)
Other versions
DE69012520D1 (de
Inventor
Kanetake Takasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69012520D1 publication Critical patent/DE69012520D1/de
Publication of DE69012520T2 publication Critical patent/DE69012520T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02513—Microstructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Junction Field-Effect Transistors (AREA)
DE69012520T 1989-11-20 1990-11-20 Halbleiterheterostruktur und Verfahren zu ihrer Herstellung. Expired - Fee Related DE69012520T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1299758A JPH03160714A (ja) 1989-11-20 1989-11-20 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
DE69012520D1 DE69012520D1 (de) 1994-10-20
DE69012520T2 true DE69012520T2 (de) 1995-02-02

Family

ID=17876621

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69012520T Expired - Fee Related DE69012520T2 (de) 1989-11-20 1990-11-20 Halbleiterheterostruktur und Verfahren zu ihrer Herstellung.

Country Status (4)

Country Link
US (1) US5107317A (de)
EP (1) EP0430562B1 (de)
JP (1) JPH03160714A (de)
DE (1) DE69012520T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04258182A (ja) * 1991-02-12 1992-09-14 Mitsubishi Electric Corp 半導体発光装置
CA2062134C (en) * 1991-05-31 1997-03-25 Ibm Heteroepitaxial layers with low defect density and arbitrary network parameter
JP3352712B2 (ja) * 1991-12-18 2002-12-03 浩 天野 窒化ガリウム系半導体素子及びその製造方法
US5326721A (en) * 1992-05-01 1994-07-05 Texas Instruments Incorporated Method of fabricating high-dielectric constant oxides on semiconductors using a GE buffer layer
US5488350A (en) * 1994-01-07 1996-01-30 Michigan State University Diamond film structures and methods related to same
US5474808A (en) * 1994-01-07 1995-12-12 Michigan State University Method of seeding diamond
US5548128A (en) * 1994-12-14 1996-08-20 The United States Of America As Represented By The Secretary Of The Air Force Direct-gap germanium-tin multiple-quantum-well electro-optical devices on silicon or germanium substrates
US6211560B1 (en) 1995-06-16 2001-04-03 The United States Of America As Represented By The Secretary Of The Air Force Voltage tunable schottky diode photoemissive infrared detector
BRPI9715293B1 (pt) 1996-06-26 2016-11-01 Osram Ag elemento de cobertura para um elemento de construção optoeletrônico
DE19638667C2 (de) * 1996-09-20 2001-05-17 Osram Opto Semiconductors Gmbh Mischfarbiges Licht abstrahlendes Halbleiterbauelement mit Lumineszenzkonversionselement
JP3268731B2 (ja) 1996-10-09 2002-03-25 沖電気工業株式会社 光電変換素子
JP3681236B2 (ja) * 1996-10-28 2005-08-10 沖電気工業株式会社 半導体装置
US6082200A (en) * 1997-09-19 2000-07-04 Board Of Trustees Operating Michigan State University Electronic device and method of use thereof
US20050196925A1 (en) * 2003-12-22 2005-09-08 Kim Sang H. Method of forming stress-relaxed SiGe buffer layer
US7902046B2 (en) * 2005-09-19 2011-03-08 The Board Of Trustees Of The Leland Stanford Junior University Thin buffer layers for SiGe growth on mismatched substrates
KR20120047583A (ko) * 2010-11-04 2012-05-14 삼성전자주식회사 태양 전지 및 이의 제조 방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5421294A (en) * 1977-07-19 1979-02-17 Mitsubishi Electric Corp Avalanche photo diode
JPS55118627A (en) * 1979-03-06 1980-09-11 Futaba Corp Compound semiconductor wafer and its manufacturing method
US4400221A (en) * 1981-07-08 1983-08-23 The United States Of America As Represented By The Secretary Of The Air Force Fabrication of gallium arsenide-germanium heteroface junction device
JPS61189621A (ja) * 1985-02-18 1986-08-23 Sharp Corp 化合物半導体装置
US4716445A (en) * 1986-01-17 1987-12-29 Nec Corporation Heterojunction bipolar transistor having a base region of germanium
US4872040A (en) * 1987-04-23 1989-10-03 International Business Machines Corporation Self-aligned heterojunction transistor
JP2716136B2 (ja) * 1988-01-14 1998-02-18 日本電気株式会社 半導体装置
US4891329A (en) * 1988-11-29 1990-01-02 University Of North Carolina Method of forming a nonsilicon semiconductor on insulator structure

Also Published As

Publication number Publication date
EP0430562A1 (de) 1991-06-05
US5107317A (en) 1992-04-21
JPH03160714A (ja) 1991-07-10
EP0430562B1 (de) 1994-09-14
DE69012520D1 (de) 1994-10-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee