DE68928370D1 - Logikschaltung mit Uebertragungsgesteuerten Addierer - Google Patents

Logikschaltung mit Uebertragungsgesteuerten Addierer

Info

Publication number
DE68928370D1
DE68928370D1 DE68928370T DE68928370T DE68928370D1 DE 68928370 D1 DE68928370 D1 DE 68928370D1 DE 68928370 T DE68928370 T DE 68928370T DE 68928370 T DE68928370 T DE 68928370T DE 68928370 D1 DE68928370 D1 DE 68928370D1
Authority
DE
Germany
Prior art keywords
logic circuit
transmission controlled
controlled adder
adder
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68928370T
Other languages
English (en)
Other versions
DE68928370T2 (de
Inventor
Gensuke Goto
Hajime Kubosawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE68928370D1 publication Critical patent/DE68928370D1/de
Publication of DE68928370T2 publication Critical patent/DE68928370T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Complex Calculations (AREA)
DE68928370T 1988-03-25 1989-03-24 Logikschaltung mit Uebertragungsgesteuerten Addierer Expired - Fee Related DE68928370T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63072635A JPH01244531A (ja) 1988-03-25 1988-03-25 論理回路

Publications (2)

Publication Number Publication Date
DE68928370D1 true DE68928370D1 (de) 1997-11-13
DE68928370T2 DE68928370T2 (de) 1998-02-05

Family

ID=13495044

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68928370T Expired - Fee Related DE68928370T2 (de) 1988-03-25 1989-03-24 Logikschaltung mit Uebertragungsgesteuerten Addierer

Country Status (4)

Country Link
EP (1) EP0334768B1 (de)
JP (1) JPH01244531A (de)
KR (1) KR920004108B1 (de)
DE (1) DE68928370T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE180068T1 (de) * 1990-04-02 1999-05-15 Advanced Micro Devices Inc Schnelladdierer mit gemischter basis
DE69228140T2 (de) * 1991-04-08 1999-08-19 Sun Microsystems Inc Verfahren und Anordnung zur Erzeugung von Übertragsignalen
KR100224278B1 (ko) * 1996-12-18 1999-10-15 윤종용 패스 트랜지스터 로직을 사용하는 조건 합 가산기 및 그것을 구비한 집적 회로
KR100351889B1 (ko) * 1998-11-13 2002-11-18 주식회사 하이닉스반도체 카스(cas)레이턴시(latency) 제어 회로
DE10225862B4 (de) * 2001-07-10 2009-12-17 Ibm Deutschland Gmbh Übertragnetz für eine Übertragauswahladdiereinheit mit ausgewogener Verzögerung zwischen Weiterleitungs- und Generierungspfad

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3993891A (en) * 1975-07-03 1976-11-23 Burroughs Corporation High speed parallel digital adder employing conditional and look-ahead approaches
JPS57147754A (en) * 1981-03-06 1982-09-11 Nippon Telegr & Teleph Corp <Ntt> Digital parallel adder
DE3346241A1 (de) * 1983-03-31 1984-10-04 Siemens AG, 1000 Berlin und 8000 München Parallelverknuepfungsschaltung mit verkuerztem uebertragsdurchlauf
JPS6055438A (ja) * 1983-09-05 1985-03-30 Matsushita Electric Ind Co Ltd ２入力加算器
NL8401308A (nl) * 1984-04-24 1985-11-18 Philips Nv Voloptelschakeling.
JPS61221822A (ja) * 1985-03-27 1986-10-02 Toshiba Corp 桁上げ選択加算器
JPS61226836A (ja) * 1985-03-30 1986-10-08 Toshiba Corp 桁上げ選択加算器
JPS62144242A (ja) * 1985-12-18 1987-06-27 Mitsubishi Electric Corp 加算回路
GB8531380D0 (en) * 1985-12-20 1986-02-05 Texas Instruments Ltd Multi-stage parallel binary adder
JPS62219027A (ja) * 1986-03-20 1987-09-26 Toshiba Corp 桁上げ先見回路
FR2596544B1 (fr) * 1986-03-28 1988-05-13 Radiotechnique Compelec Circuit arithmetique et logique

Also Published As

Publication number Publication date
EP0334768A3 (de) 1991-11-06
KR920004108B1 (ko) 1992-05-25
KR890015511A (ko) 1989-10-30
DE68928370T2 (de) 1998-02-05
EP0334768A2 (de) 1989-09-27
EP0334768B1 (de) 1997-10-08
JPH01244531A (ja) 1989-09-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee