DE68928096D1 - Integrierter Halbleiterschaltkreis - Google Patents
Integrierter HalbleiterschaltkreisInfo
- Publication number
- DE68928096D1 DE68928096D1 DE68928096T DE68928096T DE68928096D1 DE 68928096 D1 DE68928096 D1 DE 68928096D1 DE 68928096 T DE68928096 T DE 68928096T DE 68928096 T DE68928096 T DE 68928096T DE 68928096 D1 DE68928096 D1 DE 68928096D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor circuit
- integrated semiconductor
- integrated
- circuit
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63333615A JP2901188B2 (ja) | 1988-12-28 | 1988-12-28 | 半導体集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68928096D1 true DE68928096D1 (de) | 1997-07-10 |
DE68928096T2 DE68928096T2 (de) | 1997-10-16 |
Family
ID=18268032
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68928096T Expired - Fee Related DE68928096T2 (de) | 1988-12-28 | 1989-12-28 | Integrierter Halbleiterschaltkreis |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0376291B1 (de) |
JP (1) | JP2901188B2 (de) |
KR (1) | KR930007183B1 (de) |
DE (1) | DE68928096T2 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR940006676B1 (ko) * | 1991-10-14 | 1994-07-25 | 삼성전자 주식회사 | 시험회로를 내장한 기억용 반도체 집적회로 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6030170A (ja) * | 1983-07-29 | 1985-02-15 | Hitachi Ltd | 高集積読み出し専用メモリ |
JPS6120349A (ja) * | 1984-07-06 | 1986-01-29 | Hitachi Ltd | Lsi集合体 |
JPS63126263A (ja) * | 1986-11-17 | 1988-05-30 | Hitachi Ltd | 半導体集積回路装置 |
JPS63229511A (ja) * | 1987-03-19 | 1988-09-26 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
-
1988
- 1988-12-28 JP JP63333615A patent/JP2901188B2/ja not_active Expired - Lifetime
-
1989
- 1989-12-21 KR KR1019890019153A patent/KR930007183B1/ko not_active IP Right Cessation
- 1989-12-28 EP EP89124039A patent/EP0376291B1/de not_active Expired - Lifetime
- 1989-12-28 DE DE68928096T patent/DE68928096T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE68928096T2 (de) | 1997-10-16 |
EP0376291A2 (de) | 1990-07-04 |
KR900010782A (ko) | 1990-07-09 |
JPH03209757A (ja) | 1991-09-12 |
KR930007183B1 (ko) | 1993-07-31 |
JP2901188B2 (ja) | 1999-06-07 |
EP0376291B1 (de) | 1997-06-04 |
EP0376291A3 (de) | 1991-01-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |