DE68917003T2 - Verfahren zur Herstellung von Halbleiterbauelementen, die gegen Musterverunreinigungen geschützt sind. - Google Patents

Verfahren zur Herstellung von Halbleiterbauelementen, die gegen Musterverunreinigungen geschützt sind.

Info

Publication number
DE68917003T2
DE68917003T2 DE68917003T DE68917003T DE68917003T2 DE 68917003 T2 DE68917003 T2 DE 68917003T2 DE 68917003 T DE68917003 T DE 68917003T DE 68917003 T DE68917003 T DE 68917003T DE 68917003 T2 DE68917003 T2 DE 68917003T2
Authority
DE
Germany
Prior art keywords
production
protected against
semiconductor components
against pattern
pattern contamination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68917003T
Other languages
English (en)
Other versions
DE68917003D1 (de
Inventor
Hidehiko Shiraiwa
Hisatsugu Miyamaedaira Shirai
Nobuhiro Takahashi
Shinichi Nomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Original Assignee
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Fujitsu Electronics Ltd, Fujitsu Ltd filed Critical Kyushu Fujitsu Electronics Ltd
Application granted granted Critical
Publication of DE68917003D1 publication Critical patent/DE68917003D1/de
Publication of DE68917003T2 publication Critical patent/DE68917003T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/028—Dicing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)
  • Dicing (AREA)
DE68917003T 1988-04-28 1989-04-05 Verfahren zur Herstellung von Halbleiterbauelementen, die gegen Musterverunreinigungen geschützt sind. Expired - Fee Related DE68917003T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63105737A JP2575795B2 (ja) 1988-04-28 1988-04-28 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE68917003D1 DE68917003D1 (de) 1994-09-01
DE68917003T2 true DE68917003T2 (de) 1994-11-17

Family

ID=14415590

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68917003T Expired - Fee Related DE68917003T2 (de) 1988-04-28 1989-04-05 Verfahren zur Herstellung von Halbleiterbauelementen, die gegen Musterverunreinigungen geschützt sind.

Country Status (5)

Country Link
US (1) US5132252A (de)
EP (1) EP0339315B1 (de)
JP (1) JP2575795B2 (de)
KR (1) KR930000226B1 (de)
DE (1) DE68917003T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2952887B2 (ja) * 1989-05-20 1999-09-27 富士通株式会社 半導体装置およびその製造方法
JPH0831575B2 (ja) * 1993-02-12 1996-03-27 日本電気株式会社 半導体記憶装置
JP2894165B2 (ja) * 1993-07-24 1999-05-24 ヤマハ株式会社 半導体装置
JP2790416B2 (ja) * 1993-08-26 1998-08-27 沖電気工業株式会社 アライメントマーク配置方法
JP2720813B2 (ja) * 1994-10-04 1998-03-04 日本電気株式会社 半導体装置の製造方法および半導体装置
US5622899A (en) * 1996-04-22 1997-04-22 Taiwan Semiconductor Manufacturing Company Ltd. Method of fabricating semiconductor chips separated by scribe lines used for endpoint detection
US5776826A (en) * 1996-05-06 1998-07-07 International Business Machines Corporation Crack stop formation for high-productivity processes
JP4274594B2 (ja) * 1997-12-26 2009-06-10 Ｏｋｉセミコンダクタ株式会社 半導体装置の構造およびその製造方法
US6046101A (en) * 1997-12-31 2000-04-04 Intel Corporation Passivation technology combining improved adhesion in passivation and a scribe street without passivation
FR2783971B1 (fr) * 1998-09-30 2002-08-23 St Microelectronics Sa Circuit semi-conducteur comprenant des motifs en surface et procede de reglage d'un outil par rapport a cette surface
KR100293378B1 (ko) * 1999-08-31 2001-06-15 윤종용 반도체 장치의 제조방법
US7134582B2 (en) * 2001-05-29 2006-11-14 Koninklijke Philips Electronics N. V. Substrate and method of separating components from a substrate
US20030066816A1 (en) * 2001-09-17 2003-04-10 Schultz Gary A. Uniform patterning for deep reactive ion etching
US7247330B2 (en) * 2002-07-23 2007-07-24 Kraft Foods Holdings, Inc. Method for controlling microbial contamination of a vacuum-sealed food product
US20040175480A1 (en) * 2003-03-03 2004-09-09 Kraft Foods Holdings, Inc. Hop beta acid compositions for use in food products
US7001632B2 (en) * 2003-03-03 2006-02-21 Kraft Foods Holdings, Inc. Anti-listeria compositions for use in food products

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2282162A1 (fr) * 1974-08-12 1976-03-12 Radiotechnique Compelec Procede de realisation de dispositifs semiconducteurs
US4179794A (en) * 1975-07-23 1979-12-25 Nippon Gakki Seizo Kabushiki Kaisha Process of manufacturing semiconductor devices
JPS5234907A (en) * 1975-09-11 1977-03-17 Dantani Plywood Co Method of producing decorated boards with gloss change
JPS5432067A (en) * 1977-08-16 1979-03-09 Nec Corp Semiconductor device and its manufacture
JPS6041478B2 (ja) * 1979-09-10 1985-09-17 富士通株式会社 半導体レ−ザ素子の製造方法
JPS5773933A (en) * 1980-10-25 1982-05-08 Toshiba Corp Preparation of semiconductor device
JPS5949686A (ja) * 1982-09-14 1984-03-22 富士電機株式会社 自動販売機の貨幣払出制御方式
JPS6016442A (ja) * 1984-05-25 1985-01-28 Hitachi Ltd 半導体装置の製法
JPH01117030A (ja) * 1987-10-30 1989-05-09 Nec Corp 電子線位置検出基準マーク

Also Published As

Publication number Publication date
KR930000226B1 (ko) 1993-01-14
JP2575795B2 (ja) 1997-01-29
EP0339315B1 (de) 1994-07-27
EP0339315A1 (de) 1989-11-02
KR900017121A (ko) 1990-11-15
US5132252A (en) 1992-07-21
DE68917003D1 (de) 1994-09-01
JPH01276737A (ja) 1989-11-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee