JPS5773933A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5773933A
JPS5773933A JP55149898A JP14989880A JPS5773933A JP S5773933 A JPS5773933 A JP S5773933A JP 55149898 A JP55149898 A JP 55149898A JP 14989880 A JP14989880 A JP 14989880A JP S5773933 A JPS5773933 A JP S5773933A
Authority
JP
Japan
Prior art keywords
mark
electron
psg21
film
aligning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55149898A
Other languages
Japanese (ja)
Inventor
Masaki Sato
Katsuhiro Kawabuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55149898A priority Critical patent/JPS5773933A/en
Publication of JPS5773933A publication Critical patent/JPS5773933A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electron Beam Exposure (AREA)

Abstract

PURPOSE:To make clear the detection of a signal for a mark for positional alignment by electron beam scanning and to conduct thereby the positional alignment with high precision by removing the part of aligned position of an insulator film of a substrate before application of an electron-beam resist. CONSTITUTION:An opening 14 is made in SiO2 12 on a p-type Si substrate 11 and the mark 15 for aligning the position is made by etching. The film 12 being removed, a field oxidized film 16 and FET are provided by using the mark 15 by a conventional method and later are covered with PSG21. Then, a mask is prepared by applying an electron-beam resist PMMA 22a and conducting drawing and development thereon. By using this maks, the PSG21 is opened by plasma etching and subjected to high-temperature treatment in N2 and is thereby deformed. Then, a PMMA 22b is applied afresh, an electrode window is drawn and developed by using the mark 15 for aligning the position, the window is made in the PSG21 by the plasma etching, and an Al wiring 22 is attached thereto. Since the PSG in the part of the mark 15 for pigning the position is removed, the SN ratio of a position detection signal at the time of the electron-beam scanning is not deteriorated and there is no decline in the precision of overlapping of patterns.
JP55149898A 1980-10-25 1980-10-25 Preparation of semiconductor device Pending JPS5773933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55149898A JPS5773933A (en) 1980-10-25 1980-10-25 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55149898A JPS5773933A (en) 1980-10-25 1980-10-25 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5773933A true JPS5773933A (en) 1982-05-08

Family

ID=15485017

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55149898A Pending JPS5773933A (en) 1980-10-25 1980-10-25 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5773933A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132252A (en) * 1988-04-28 1992-07-21 Fujitsu Limited Method for fabricating semiconductor devices that prevents pattern contamination

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132252A (en) * 1988-04-28 1992-07-21 Fujitsu Limited Method for fabricating semiconductor devices that prevents pattern contamination

Similar Documents

Publication Publication Date Title
EP0410385B1 (en) Method of manufacturing a semiconductor device comprising a T-gate
JPS56122130A (en) Method for forming pattern of thin film transistor
EP0095209A3 (en) Method of forming a resist mask resistant to plasma etching
EP0072933A1 (en) Method for photolithographic pattern generation in a photoresist layer
JPS5773933A (en) Preparation of semiconductor device
JPS5623783A (en) Formation of electrode for semiconductor device
JPS6468932A (en) Dry etching
JPS54116883A (en) Electron beam exposure method
WO1983003485A1 (en) Electron beam-optical hybrid lithographic resist process
JPS57177525A (en) Etching method for silicon oxide
JPS5680130A (en) Manufacture of semiconductor device
US5212117A (en) Method of manufacturing a semiconductor device contact structure using lift
JPS55128830A (en) Method of working photoresist film
JPS6430220A (en) Alignment mark
JPS57180176A (en) Manufacturing method for semiconductor device
JPS6252850B2 (en)
JPS57166085A (en) Manufacture of semiconductor device
JPS57124443A (en) Forming method for electrode layer
KR100198599B1 (en) Alligning method for semiconductor device fabrication
JPS54162490A (en) Manufacture of semiconductor device
JPS58145125A (en) Formation of resist mask
KR100442288B1 (en) Cell mask of semiconductor device and method for fabricating the same
JPS55138835A (en) Method of forming photoresist pattern
JPS61270823A (en) Manufacture of semiconductor device
JPS5780718A (en) Manufacture of semiconductor integrated circuit device