DE60239771D1 - Verfahren zur Herstellung eines Gate-Dielektrikums mit Gebieten hoher und niedriger Dielektrizitätskonstante - Google Patents

Verfahren zur Herstellung eines Gate-Dielektrikums mit Gebieten hoher und niedriger Dielektrizitätskonstante

Info

Publication number
DE60239771D1
DE60239771D1 DE60239771T DE60239771T DE60239771D1 DE 60239771 D1 DE60239771 D1 DE 60239771D1 DE 60239771 T DE60239771 T DE 60239771T DE 60239771 T DE60239771 T DE 60239771T DE 60239771 D1 DE60239771 D1 DE 60239771D1
Authority
DE
Germany
Prior art keywords
dielectric layer
gate opening
low
fabricating
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60239771T
Other languages
English (en)
Inventor
Lap Chan
Elgin Quek
Ravi Sundaresan
Yang Pan
James Yong Meng Lee
Ying Keung Leung
Yelehanka Ramachandramurthy Pradeep
Jia Zhen Zheng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Singapore Pte Ltd
Original Assignee
Chartered Semiconductor Manufacturing Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chartered Semiconductor Manufacturing Pte Ltd filed Critical Chartered Semiconductor Manufacturing Pte Ltd
Application granted granted Critical
Publication of DE60239771D1 publication Critical patent/DE60239771D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/512—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being parallel to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Formation Of Insulating Films (AREA)
  • Bipolar Transistors (AREA)
  • Thin Film Transistor (AREA)
DE60239771T 2001-01-26 2002-01-25 Verfahren zur Herstellung eines Gate-Dielektrikums mit Gebieten hoher und niedriger Dielektrizitätskonstante Expired - Lifetime DE60239771D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/769,810 US6406945B1 (en) 2001-01-26 2001-01-26 Method for forming a transistor gate dielectric with high-K and low-K regions

Publications (1)

Publication Number Publication Date
DE60239771D1 true DE60239771D1 (de) 2011-06-01

Family

ID=25086565

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60239771T Expired - Lifetime DE60239771D1 (de) 2001-01-26 2002-01-25 Verfahren zur Herstellung eines Gate-Dielektrikums mit Gebieten hoher und niedriger Dielektrizitätskonstante

Country Status (7)

Country Link
US (1) US6406945B1 (de)
EP (1) EP1227514B1 (de)
JP (1) JP2002289851A (de)
AT (1) ATE506694T1 (de)
DE (1) DE60239771D1 (de)
SG (1) SG99379A1 (de)
TW (1) TW488018B (de)

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US6509612B2 (en) * 2001-05-04 2003-01-21 International Business Machines Corporation High dielectric constant materials as gate dielectrics (insulators)
US20020179982A1 (en) * 2001-05-29 2002-12-05 United Microelectronics Corp. MOS field effect transistor structure and method of manufacture
US6762463B2 (en) * 2001-06-09 2004-07-13 Advanced Micro Devices, Inc. MOSFET with SiGe source/drain regions and epitaxial gate dielectric
US6713357B1 (en) * 2001-12-20 2004-03-30 Advanced Micro Devices, Inc. Method to reduce parasitic capacitance of MOS transistors
US6617209B1 (en) * 2002-02-22 2003-09-09 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US7187031B2 (en) * 2002-05-31 2007-03-06 Sharp Kabushiki Kaisha Semiconductor device having a low dielectric constant film and manufacturing method thereof
US6806149B2 (en) * 2002-09-26 2004-10-19 Texas Instruments Incorporated Sidewall processes using alkylsilane precursors for MOS transistor fabrication
US6746900B1 (en) * 2003-02-19 2004-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a semiconductor device having high-K gate dielectric material
KR100486654B1 (ko) 2003-08-07 2005-05-03 동부아남반도체 주식회사 반도체의 삼중 게이트 산화막 형성방법
US20050259467A1 (en) * 2004-05-18 2005-11-24 Micron Technology, Inc. Split gate flash memory cell with ballistic injection
US7196935B2 (en) * 2004-05-18 2007-03-27 Micron Technolnology, Inc. Ballistic injection NROM flash memory
US20060043462A1 (en) * 2004-08-27 2006-03-02 Micron Technology, Inc. Stepped gate configuration for non-volatile memory
DE102004044667A1 (de) * 2004-09-15 2006-03-16 Infineon Technologies Ag Halbleiterbauelement sowie zugehöriges Herstellungsverfahren
US20060157750A1 (en) * 2005-01-20 2006-07-20 Samsung Electronics Co., Ltd. Semiconductor device having etch-resistant L-shaped spacer and fabrication method thereof
KR100647314B1 (ko) * 2005-01-31 2006-11-23 삼성전자주식회사 나노 임프린트 리소그래피용 정렬시스템 및 이를 채용한임프린트 리소그래피 방법
US7365378B2 (en) * 2005-03-31 2008-04-29 International Business Machines Corporation MOSFET structure with ultra-low K spacer
KR100596802B1 (ko) * 2005-05-27 2006-07-04 주식회사 하이닉스반도체 반도체 소자의 제조방법
US7349196B2 (en) * 2005-06-17 2008-03-25 Industrial Technology Research Institute Composite distributed dielectric structure
TW200735222A (en) 2006-03-15 2007-09-16 Promos Technologies Inc Multi-steps gate structure and method for preparing the same
TWI312177B (en) 2006-03-15 2009-07-11 Promos Technologies Inc Recessed gate structure and method for preparing the same
JP2009070849A (ja) * 2007-09-10 2009-04-02 Rohm Co Ltd 半導体装置
US8420460B2 (en) 2008-03-26 2013-04-16 International Business Machines Corporation Method, structure and design structure for customizing history effects of SOI circuits
US8410554B2 (en) * 2008-03-26 2013-04-02 International Business Machines Corporation Method, structure and design structure for customizing history effects of SOI circuits
US7964467B2 (en) * 2008-03-26 2011-06-21 International Business Machines Corporation Method, structure and design structure for customizing history effects of soi circuits
JP2012060063A (ja) 2010-09-13 2012-03-22 Toshiba Corp 半導体装置及びその製造方法
JP2012099517A (ja) 2010-10-29 2012-05-24 Sony Corp 半導体装置及び半導体装置の製造方法
KR101737490B1 (ko) * 2010-11-11 2017-05-18 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN102479746B (zh) * 2010-11-29 2013-11-20 中芯国际集成电路制造(上海)有限公司 减少金属栅电极和接触孔之间寄生电容的方法
US8642424B2 (en) 2011-07-12 2014-02-04 International Business Machines Corporation Replacement metal gate structure and methods of manufacture
US8941177B2 (en) 2012-06-27 2015-01-27 International Business Machines Corporation Semiconductor devices having different gate oxide thicknesses
KR102167625B1 (ko) * 2013-10-24 2020-10-19 삼성전자주식회사 반도체 장치 및 그 제조 방법
EP3179514B1 (de) 2015-12-11 2024-01-24 IMEC vzw Transistorvorrichtung mit einer reduzierten injektionswirkung von heissen ladungsträgern
JP7232764B2 (ja) 2017-08-04 2023-03-03 株式会社半導体エネルギー研究所 半導体装置
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Also Published As

Publication number Publication date
TW488018B (en) 2002-05-21
EP1227514A2 (de) 2002-07-31
EP1227514A3 (de) 2003-12-03
JP2002289851A (ja) 2002-10-04
SG99379A1 (en) 2003-10-27
ATE506694T1 (de) 2011-05-15
EP1227514B1 (de) 2011-04-20
US6406945B1 (en) 2002-06-18

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