DE60224131D1 - Leiterrahmen-Packung in Chipgrösse - Google Patents

Leiterrahmen-Packung in Chipgrösse

Info

Publication number
DE60224131D1
DE60224131D1 DE60224131T DE60224131T DE60224131D1 DE 60224131 D1 DE60224131 D1 DE 60224131D1 DE 60224131 T DE60224131 T DE 60224131T DE 60224131 T DE60224131 T DE 60224131T DE 60224131 D1 DE60224131 D1 DE 60224131D1
Authority
DE
Germany
Prior art keywords
lead frame
chip size
frame pack
pack
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60224131T
Other languages
English (en)
Other versions
DE60224131T2 (de
Inventor
William James Palmteer
Philip Joseph Beucler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MACOM Technology Solutions Holdings Inc
Original Assignee
Tyco Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tyco Electronics Corp filed Critical Tyco Electronics Corp
Application granted granted Critical
Publication of DE60224131D1 publication Critical patent/DE60224131D1/de
Publication of DE60224131T2 publication Critical patent/DE60224131T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
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    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
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    • H01L2924/01042Molybdenum [Mo]
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
DE60224131T 2001-04-16 2002-04-16 Leiterrahmen-Packung in Chipgrösse Expired - Fee Related DE60224131T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US28402901P 2001-04-16 2001-04-16
US284029P 2001-04-16
US966222 2001-09-28
US09/966,222 US7034382B2 (en) 2001-04-16 2001-09-28 Leadframe-based chip scale package

Publications (2)

Publication Number Publication Date
DE60224131D1 true DE60224131D1 (de) 2008-01-31
DE60224131T2 DE60224131T2 (de) 2008-12-04

Family

ID=26962373

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60224131T Expired - Fee Related DE60224131T2 (de) 2001-04-16 2002-04-16 Leiterrahmen-Packung in Chipgrösse

Country Status (3)

Country Link
US (1) US7034382B2 (de)
EP (1) EP1253640B1 (de)
DE (1) DE60224131T2 (de)

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US7960819B2 (en) * 2006-07-13 2011-06-14 Cree, Inc. Leadframe-based packages for solid state emitting devices
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JP2008078445A (ja) * 2006-09-22 2008-04-03 Yamaha Corp リードフレーム
DE102006060429B4 (de) * 2006-12-20 2013-08-22 Epcos Ag Elektrisches Bauelement mit Leadframe-Strukturen
KR101391924B1 (ko) * 2007-01-05 2014-05-07 페어차일드코리아반도체 주식회사 반도체 패키지
US8067825B2 (en) * 2007-09-28 2011-11-29 Stats Chippac Ltd. Integrated circuit package system with multiple die
TWI392065B (zh) * 2009-06-08 2013-04-01 Cyntec Co Ltd 電子元件封裝模組
JP6210818B2 (ja) * 2013-09-30 2017-10-11 三菱電機株式会社 半導体装置およびその製造方法
KR102179297B1 (ko) 2014-07-09 2020-11-18 삼성전자주식회사 모노 패키지 내에서 인터커넥션을 가지는 반도체 장치 및 그에 따른 제조 방법
KR102229942B1 (ko) 2014-07-09 2021-03-22 삼성전자주식회사 멀티 다이들을 갖는 멀티 채널 반도체 장치의 동작 방법 및 그에 따른 반도체 장치
JP6252412B2 (ja) 2014-09-10 2017-12-27 三菱電機株式会社 半導体装置
CN113823569A (zh) * 2020-06-18 2021-12-21 吴江华丰电子科技有限公司 一种制作电子装置的方法

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EP1253640A2 (de) 2002-10-30
EP1253640A3 (de) 2004-03-03
DE60224131T2 (de) 2008-12-04
US7034382B2 (en) 2006-04-25
US20020149091A1 (en) 2002-10-17
EP1253640B1 (de) 2007-12-19

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