DE60224131D1 - Leiterrahmen-Packung in Chipgrösse - Google Patents

Leiterrahmen-Packung in Chipgrösse

Info

Publication number
DE60224131D1
DE60224131D1 DE60224131T DE60224131T DE60224131D1 DE 60224131 D1 DE60224131 D1 DE 60224131D1 DE 60224131 T DE60224131 T DE 60224131T DE 60224131 T DE60224131 T DE 60224131T DE 60224131 D1 DE60224131 D1 DE 60224131D1
Authority
DE
Germany
Prior art keywords
lead frame
chip size
frame pack
pack
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60224131T
Other languages
English (en)
Other versions
DE60224131T2 (de
Inventor
William James Palmteer
Philip Joseph Beucler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MACOM Technology Solutions Holdings Inc
Original Assignee
Tyco Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tyco Electronics Corp filed Critical Tyco Electronics Corp
Application granted granted Critical
Publication of DE60224131D1 publication Critical patent/DE60224131D1/de
Publication of DE60224131T2 publication Critical patent/DE60224131T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/06164—Random array, i.e. array with no symmetry covering only portions of the surface to be connected
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
DE60224131T 2001-04-16 2002-04-16 Leiterrahmen-Packung in Chipgrösse Expired - Fee Related DE60224131T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US28402901P 2001-04-16 2001-04-16
US284029P 2001-04-16
US966222 2001-09-28
US09/966,222 US7034382B2 (en) 2001-04-16 2001-09-28 Leadframe-based chip scale package

Publications (2)

Publication Number Publication Date
DE60224131D1 true DE60224131D1 (de) 2008-01-31
DE60224131T2 DE60224131T2 (de) 2008-12-04

Family

ID=26962373

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60224131T Expired - Fee Related DE60224131T2 (de) 2001-04-16 2002-04-16 Leiterrahmen-Packung in Chipgrösse

Country Status (3)

Country Link
US (1) US7034382B2 (de)
EP (1) EP1253640B1 (de)
DE (1) DE60224131T2 (de)

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US6984881B2 (en) * 2003-06-16 2006-01-10 Sandisk Corporation Stackable integrated circuit package and method therefor
US20050248041A1 (en) * 2004-05-05 2005-11-10 Atm Technology Singapore Pte Ltd Electronic device with high lead density
DE102004025773B4 (de) * 2004-05-26 2008-08-21 Siemens Ag Elektronisches Bauelement mit thermisch voneinander isolierten Bereichen
US20060267173A1 (en) * 2005-05-26 2006-11-30 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
US7790504B2 (en) * 2006-03-10 2010-09-07 Stats Chippac Ltd. Integrated circuit package system
US8044418B2 (en) 2006-07-13 2011-10-25 Cree, Inc. Leadframe-based packages for solid state light emitting devices
US7960819B2 (en) * 2006-07-13 2011-06-14 Cree, Inc. Leadframe-based packages for solid state emitting devices
US7977773B1 (en) * 2006-07-17 2011-07-12 Marvell International Ltd. Leadframe including die paddle apertures for reducing delamination
JP2008078445A (ja) * 2006-09-22 2008-04-03 Yamaha Corp リードフレーム
DE102006060429B4 (de) * 2006-12-20 2013-08-22 Epcos Ag Elektrisches Bauelement mit Leadframe-Strukturen
KR101391924B1 (ko) * 2007-01-05 2014-05-07 페어차일드코리아반도체 주식회사 반도체 패키지
US8067825B2 (en) * 2007-09-28 2011-11-29 Stats Chippac Ltd. Integrated circuit package system with multiple die
TWI392065B (zh) * 2009-06-08 2013-04-01 Cyntec Co Ltd 電子元件封裝模組
JP6210818B2 (ja) * 2013-09-30 2017-10-11 三菱電機株式会社 半導体装置およびその製造方法
KR102179297B1 (ko) 2014-07-09 2020-11-18 삼성전자주식회사 모노 패키지 내에서 인터커넥션을 가지는 반도체 장치 및 그에 따른 제조 방법
KR102229942B1 (ko) 2014-07-09 2021-03-22 삼성전자주식회사 멀티 다이들을 갖는 멀티 채널 반도체 장치의 동작 방법 및 그에 따른 반도체 장치
JP6252412B2 (ja) 2014-09-10 2017-12-27 三菱電機株式会社 半導体装置
CN113823569A (zh) * 2020-06-18 2021-12-21 吴江华丰电子科技有限公司 一种制作电子装置的方法

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EP1253640A2 (de) 2002-10-30
EP1253640A3 (de) 2004-03-03
DE60224131T2 (de) 2008-12-04
US7034382B2 (en) 2006-04-25
US20020149091A1 (en) 2002-10-17
EP1253640B1 (de) 2007-12-19

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