DE60218945T2 - Speicheranordnung mit Dünnfilmtransistoren - Google Patents

Speicheranordnung mit Dünnfilmtransistoren Download PDF

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Publication number
DE60218945T2
DE60218945T2 DE60218945T DE60218945T DE60218945T2 DE 60218945 T2 DE60218945 T2 DE 60218945T2 DE 60218945 T DE60218945 T DE 60218945T DE 60218945 T DE60218945 T DE 60218945T DE 60218945 T2 DE60218945 T2 DE 60218945T2
Authority
DE
Germany
Prior art keywords
gate
memory cell
memory
applying
insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60218945T
Other languages
German (de)
English (en)
Other versions
DE60218945D1 (de
Inventor
Ping Palo Alto Mei
James R. Jr. Palo Alto Eaton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Publication of DE60218945D1 publication Critical patent/DE60218945D1/de
Application granted granted Critical
Publication of DE60218945T2 publication Critical patent/DE60218945T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Thin Film Transistor (AREA)
  • Read Only Memory (AREA)
DE60218945T 2001-08-23 2002-08-19 Speicheranordnung mit Dünnfilmtransistoren Expired - Lifetime DE60218945T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/934,548 US6864529B2 (en) 2001-08-23 2001-08-23 Thin film transistor memory device
US934548 2001-08-23

Publications (2)

Publication Number Publication Date
DE60218945D1 DE60218945D1 (de) 2007-05-03
DE60218945T2 true DE60218945T2 (de) 2007-10-18

Family

ID=25465715

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60218945T Expired - Lifetime DE60218945T2 (de) 2001-08-23 2002-08-19 Speicheranordnung mit Dünnfilmtransistoren

Country Status (7)

Country Link
US (2) US6864529B2 (enExample)
EP (1) EP1286357B1 (enExample)
JP (1) JP2003152118A (enExample)
KR (1) KR20030017396A (enExample)
CN (1) CN1407615A (enExample)
DE (1) DE60218945T2 (enExample)
TW (1) TWI240273B (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6864529B2 (en) * 2001-08-23 2005-03-08 Hewlett-Packard Development Company, L.P. Thin film transistor memory device
KR100951898B1 (ko) * 2002-12-09 2010-04-09 삼성전자주식회사 포토레지스트 제거용 스트리핑 조성물 및 이를 사용한액정 표시 장치의 박막 트랜지스터 기판의 제조방법
DE102005017071B4 (de) * 2004-12-29 2011-09-15 Hynix Semiconductor Inc. Schwebe-Gate-Speichereinrichtung
JP2006245280A (ja) * 2005-03-03 2006-09-14 Matsushita Electric Ind Co Ltd 電界効果トランジスタ及びその動作方法
US7622022B2 (en) 2006-06-01 2009-11-24 Benny J Skaggs Surface treatment of substrate or paper/paperboard products using optical brightening agent
US8809932B2 (en) * 2007-03-26 2014-08-19 Samsung Electronics Co., Ltd. Semiconductor memory device, method of fabricating the same, and devices employing the semiconductor memory device
US7859895B2 (en) * 2008-06-06 2010-12-28 Ovonyx, Inc. Standalone thin film memory
US8416609B2 (en) 2010-02-15 2013-04-09 Micron Technology, Inc. Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, methods of writing to and reading from a memory cell, and computer systems
US8437174B2 (en) * 2010-02-15 2013-05-07 Micron Technology, Inc. Memcapacitor devices, field effect transistor devices, non-volatile memory arrays, and methods of programming
US8634224B2 (en) 2010-08-12 2014-01-21 Micron Technology, Inc. Memory cells, non-volatile memory arrays, methods of operating memory cells, methods of writing to and reading from a memory cell, and methods of programming a memory cell
US8877531B2 (en) 2010-09-27 2014-11-04 Applied Materials, Inc. Electronic apparatus
WO2013112511A2 (en) 2012-01-23 2013-08-01 International Paper Company Separated treatment of paper substrate with multivalent metal salts and obas
WO2018182711A1 (en) * 2017-03-31 2018-10-04 Intel Corporation Thin film transistors with multiple channel layers
WO2018182714A1 (en) * 2017-03-31 2018-10-04 Intel Corporation Top-gated thin film transistors with multiple channel layers

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4203158A (en) 1978-02-24 1980-05-13 Intel Corporation Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same
US4387503A (en) 1981-08-13 1983-06-14 Mostek Corporation Method for programming circuit elements in integrated circuits
US4939559A (en) * 1981-12-14 1990-07-03 International Business Machines Corporation Dual electron injector structures using a conductive oxide between injectors
JPS61208865A (ja) * 1985-03-13 1986-09-17 Mitsubishi Electric Corp 半導体記憶装置
GB8910854D0 (en) 1989-05-11 1989-06-28 British Petroleum Co Plc Semiconductor device
US5276344A (en) * 1990-04-27 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Field effect transistor having impurity regions of different depths and manufacturing method thereof
US6143582A (en) 1990-12-31 2000-11-07 Kopin Corporation High density electronic circuit modules
JP2817500B2 (ja) 1992-02-07 1998-10-30 日本電気株式会社 不揮発性半導体記憶装置
JPH0669515A (ja) 1992-08-19 1994-03-11 Fujitsu Ltd 半導体記憶装置
US5738731A (en) 1993-11-19 1998-04-14 Mega Chips Corporation Photovoltaic device
JP3745392B2 (ja) 1994-05-26 2006-02-15 株式会社ルネサステクノロジ 半導体装置
JP2928114B2 (ja) * 1994-11-29 1999-08-03 モトローラ株式会社 多層フローティングゲート構造のマルチビット対応セルを有する不揮発性メモリ及びそのプログラム方法
JPH08222648A (ja) * 1995-02-14 1996-08-30 Canon Inc 記憶装置
US6362504B1 (en) * 1995-11-22 2002-03-26 Philips Electronics North America Corporation Contoured nonvolatile memory cell
US5817550A (en) 1996-03-05 1998-10-06 Regents Of The University Of California Method for formation of thin film transistors on plastic substrates
US6005806A (en) 1996-03-14 1999-12-21 Altera Corporation Nonvolatile configuration cells and cell arrays
US5742555A (en) 1996-08-20 1998-04-21 Micron Technology, Inc. Method of anti-fuse repair
US5981404A (en) 1996-11-22 1999-11-09 United Microelectronics Corp. Multilayer ONO structure
US5787042A (en) 1997-03-18 1998-07-28 Micron Technology, Inc. Method and apparatus for reading out a programmable resistor memory
US5912840A (en) 1997-08-21 1999-06-15 Micron Technology Memory cell architecture utilizing a transistor having a dual access gate
US6005270A (en) 1997-11-10 1999-12-21 Sony Corporation Semiconductor nonvolatile memory device and method of production of same
KR100261221B1 (ko) 1997-12-31 2000-07-01 윤종용 단일 트랜지스터 셀 및 이를 제조하는 방법 및 이 소자로 구성된 메모리 회로와 이를 구동하는 방법
JP4501164B2 (ja) 1998-05-01 2010-07-14 ソニー株式会社 半導体記憶装置
US6242770B1 (en) 1998-08-31 2001-06-05 Gary Bela Bronner Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method for forming the same
US6420752B1 (en) * 2000-02-11 2002-07-16 Advanced Micro Devices, Inc. Semiconductor device with self-aligned contacts using a liner oxide layer
JP2001357682A (ja) * 2000-06-12 2001-12-26 Sony Corp メモリシステムおよびそのプログラム方法
US6864529B2 (en) * 2001-08-23 2005-03-08 Hewlett-Packard Development Company, L.P. Thin film transistor memory device

Also Published As

Publication number Publication date
DE60218945D1 (de) 2007-05-03
US20050157547A1 (en) 2005-07-21
US7161838B2 (en) 2007-01-09
TWI240273B (en) 2005-09-21
JP2003152118A (ja) 2003-05-23
US20030045037A1 (en) 2003-03-06
EP1286357A1 (en) 2003-02-26
US6864529B2 (en) 2005-03-08
CN1407615A (zh) 2003-04-02
KR20030017396A (ko) 2003-03-03
EP1286357B1 (en) 2007-03-21

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, US

8364 No opposition during term of opposition