DE60212247D1 - Halbleiterspeicherbauelement, - system und Zugriffsverfahren - Google Patents

Halbleiterspeicherbauelement, - system und Zugriffsverfahren

Info

Publication number
DE60212247D1
DE60212247D1 DE60212247T DE60212247T DE60212247D1 DE 60212247 D1 DE60212247 D1 DE 60212247D1 DE 60212247 T DE60212247 T DE 60212247T DE 60212247 T DE60212247 T DE 60212247T DE 60212247 D1 DE60212247 D1 DE 60212247D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
access method
access
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60212247T
Other languages
English (en)
Inventor
Shinichi Shionoya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Application granted granted Critical
Publication of DE60212247D1 publication Critical patent/DE60212247D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/781—Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder
DE60212247T 2001-04-19 2002-04-19 Halbleiterspeicherbauelement, - system und Zugriffsverfahren Expired - Lifetime DE60212247D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001120853A JP2002319296A (ja) 2001-04-19 2001-04-19 半導体装置及びシステム及び方法

Publications (1)

Publication Number Publication Date
DE60212247D1 true DE60212247D1 (de) 2006-07-27

Family

ID=18970830

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60212247T Expired - Lifetime DE60212247D1 (de) 2001-04-19 2002-04-19 Halbleiterspeicherbauelement, - system und Zugriffsverfahren

Country Status (5)

Country Link
US (1) US6504771B2 (de)
EP (1) EP1251525B1 (de)
JP (1) JP2002319296A (de)
KR (1) KR100489999B1 (de)
DE (1) DE60212247D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7123512B2 (en) * 2002-07-19 2006-10-17 Micron Technology, Inc. Contiguous block addressing scheme
JP2006134997A (ja) 2004-11-04 2006-05-25 Fujitsu Ltd プログラム可能論理デバイス
CN101091223B (zh) * 2004-12-24 2011-06-08 斯班逊有限公司 施加偏压至储存器件的方法与装置
KR100865802B1 (ko) * 2007-07-25 2008-10-28 주식회사 하이닉스반도체 낸드 플래시 메모리 소자 및 그 동작 방법
US7984329B2 (en) * 2007-09-04 2011-07-19 International Business Machines Corporation System and method for providing DRAM device-level repair via address remappings external to the device
KR20120120769A (ko) * 2011-04-25 2012-11-02 에스케이하이닉스 주식회사 메모리와 메모리 콘트롤러를 포함하는 메모리 시스템, 및 이의 동작방법
JP6221762B2 (ja) 2014-01-16 2017-11-01 富士通株式会社 記憶装置、記憶方法及び制御装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5841500A (ja) * 1981-08-24 1983-03-10 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン 欠陥分離用デコ−ダ
US5550394A (en) * 1993-06-18 1996-08-27 Texas Instruments Incorporated Semiconductor memory device and defective memory cell correction circuit
US5621690A (en) * 1995-04-28 1997-04-15 Intel Corporation Nonvolatile memory blocking architecture and redundancy
KR0172382B1 (ko) * 1995-12-21 1999-03-30 김광호 메모리셀 어레이 블럭의 재배치가 가능한 반도체 메모리 장치
JP2956634B2 (ja) * 1997-01-27 1999-10-04 日本電気株式会社 半導体記憶装置の冗長アドレス選択方式および半導体記憶装置
JPH10242288A (ja) 1997-02-25 1998-09-11 Hitachi Ltd 半導体装置及びシステム
JP3749789B2 (ja) * 1998-06-08 2006-03-01 株式会社東芝 半導体記憶装置
JP2000067577A (ja) * 1998-06-10 2000-03-03 Mitsubishi Electric Corp 同期型半導体記憶装置
JP4603111B2 (ja) * 1999-06-17 2010-12-22 富士通セミコンダクター株式会社 半導体記憶装置
DE19917588A1 (de) * 1999-04-19 2000-11-02 Siemens Ag Halbleiterspeicheranordnung mit BIST

Also Published As

Publication number Publication date
EP1251525A1 (de) 2002-10-23
KR20020082431A (ko) 2002-10-31
KR100489999B1 (ko) 2005-05-17
JP2002319296A (ja) 2002-10-31
EP1251525B1 (de) 2006-06-14
US20020154559A1 (en) 2002-10-24
US6504771B2 (en) 2003-01-07

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