DE60206232T2 - Schaltung und Methode zum Regeln einer Taktverschiebung in einem Kommunikationssystem - Google Patents
Schaltung und Methode zum Regeln einer Taktverschiebung in einem Kommunikationssystem Download PDFInfo
- Publication number
- DE60206232T2 DE60206232T2 DE60206232T DE60206232T DE60206232T2 DE 60206232 T2 DE60206232 T2 DE 60206232T2 DE 60206232 T DE60206232 T DE 60206232T DE 60206232 T DE60206232 T DE 60206232T DE 60206232 T2 DE60206232 T2 DE 60206232T2
- Authority
- DE
- Germany
- Prior art keywords
- clock
- data
- input
- offset
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 17
- 238000004891 communication Methods 0.000 title description 18
- 230000001934 delay Effects 0.000 claims description 14
- 238000012544 monitoring process Methods 0.000 claims 1
- 230000010363 phase shift Effects 0.000 description 15
- 230000007704 transition Effects 0.000 description 10
- 230000005540 biological transmission Effects 0.000 description 9
- 238000012360 testing method Methods 0.000 description 8
- 238000013459 approach Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 2
- 230000008713 feedback mechanism Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 238000012937 correction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
- G01R31/3191—Calibration
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31937—Timing aspects, e.g. measuring propagation delay
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US967443 | 2001-09-28 | ||
| US09/967,443 US6823466B2 (en) | 2001-09-28 | 2001-09-28 | Circuit and method for adjusting the clock skew in a communications system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE60206232D1 DE60206232D1 (de) | 2005-10-27 |
| DE60206232T2 true DE60206232T2 (de) | 2006-06-22 |
Family
ID=25512800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60206232T Expired - Fee Related DE60206232T2 (de) | 2001-09-28 | 2002-07-25 | Schaltung und Methode zum Regeln einer Taktverschiebung in einem Kommunikationssystem |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6823466B2 (enExample) |
| EP (1) | EP1298443B1 (enExample) |
| JP (1) | JP2003198521A (enExample) |
| DE (1) | DE60206232T2 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6823466B2 (en) * | 2001-09-28 | 2004-11-23 | Agilent Technologies, Inc. | Circuit and method for adjusting the clock skew in a communications system |
| US6973603B2 (en) * | 2002-06-28 | 2005-12-06 | Intel Corporation | Method and apparatus for optimizing timing for a multi-drop bus |
| ES2551427T3 (es) | 2012-02-06 | 2015-11-19 | William L. Pridgen | Combinación de famciclovir y celecoxib para síndromes somáticos funcionales |
| CN104243222A (zh) * | 2013-06-06 | 2014-12-24 | 鸿富锦精密工业（深圳）有限公司 | 网络设备性能测试方法及测试装置和测试系统 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4550405A (en) * | 1982-12-23 | 1985-10-29 | Fairchild Camera And Instrument Corporation | Deskew circuit for automatic test equipment |
| US4546269A (en) * | 1983-12-01 | 1985-10-08 | Control Data Corporation | Method and apparatus for optimally tuning clock signals for digital computers |
| US5157277A (en) * | 1990-12-28 | 1992-10-20 | Compaq Computer Corporation | Clock buffer with adjustable delay and fixed duty cycle output |
| JPH0832425A (ja) * | 1994-07-18 | 1996-02-02 | Fujitsu Ltd | データ読み取りタイミング可変回路 |
| US5856753A (en) * | 1996-03-29 | 1999-01-05 | Cypress Semiconductor Corp. | Output circuit for 3V/5V clock chip duty cycle adjustments |
| US6108794A (en) * | 1998-02-24 | 2000-08-22 | Agilent Technologies | Signal comparison system and method for improving data analysis by determining transitions of a data signal with respect to a clock signal |
| US6239629B1 (en) * | 1999-04-29 | 2001-05-29 | Agilent Technologies, Inc. | Signal comparison system and method for detecting and correcting timing errors |
| US6687844B1 (en) * | 2000-09-28 | 2004-02-03 | Intel Corporation | Method for correcting clock duty cycle skew by adjusting a delayed clock signal according to measured differences in time intervals between phases of original clock signal |
| US6823466B2 (en) * | 2001-09-28 | 2004-11-23 | Agilent Technologies, Inc. | Circuit and method for adjusting the clock skew in a communications system |
-
2001
- 2001-09-28 US US09/967,443 patent/US6823466B2/en not_active Expired - Fee Related
-
2002
- 2002-07-25 DE DE60206232T patent/DE60206232T2/de not_active Expired - Fee Related
- 2002-07-25 EP EP02016652A patent/EP1298443B1/en not_active Expired - Lifetime
- 2002-09-19 JP JP2002273199A patent/JP2003198521A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP1298443A3 (en) | 2004-06-16 |
| US6823466B2 (en) | 2004-11-23 |
| DE60206232D1 (de) | 2005-10-27 |
| US20030065988A1 (en) | 2003-04-03 |
| EP1298443A2 (en) | 2003-04-02 |
| EP1298443B1 (en) | 2005-09-21 |
| JP2003198521A (ja) | 2003-07-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8327 | Change in the person/name/address of the patent owner |
Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D. STAATES, US |
|
| 8339 | Ceased/non-payment of the annual fee |