DE69431266T2 - Pufferschaltungen - Google Patents

Pufferschaltungen

Info

Publication number
DE69431266T2
DE69431266T2 DE69431266T DE69431266T DE69431266T2 DE 69431266 T2 DE69431266 T2 DE 69431266T2 DE 69431266 T DE69431266 T DE 69431266T DE 69431266 T DE69431266 T DE 69431266T DE 69431266 T2 DE69431266 T2 DE 69431266T2
Authority
DE
Germany
Prior art keywords
buffer circuits
circuits
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69431266T
Other languages
English (en)
Other versions
DE69431266D1 (de
Inventor
Stephen C Horne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69431266D1 publication Critical patent/DE69431266D1/de
Publication of DE69431266T2 publication Critical patent/DE69431266T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
DE69431266T 1993-02-08 1994-01-21 Pufferschaltungen Expired - Lifetime DE69431266T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/014,955 US5444406A (en) 1993-02-08 1993-02-08 Self-adjusting variable drive strength buffer circuit and method for controlling the drive strength of a buffer circuit

Publications (2)

Publication Number Publication Date
DE69431266D1 DE69431266D1 (de) 2002-10-10
DE69431266T2 true DE69431266T2 (de) 2003-05-28

Family

ID=21768764

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69431266T Expired - Lifetime DE69431266T2 (de) 1993-02-08 1994-01-21 Pufferschaltungen

Country Status (4)

Country Link
US (1) US5444406A (de)
EP (1) EP0611053B1 (de)
JP (1) JPH07326949A (de)
DE (1) DE69431266T2 (de)

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KR960003042B1 (ko) * 1992-05-26 1996-03-04 가부시끼가이샤 도시바 데이타 출력 장치
US5614905A (en) * 1994-01-25 1997-03-25 Crane; Ronald C. High speed serial digital data to analog signal converter
EP0735687A3 (de) * 1995-03-31 1998-03-25 STMicroelectronics, Inc. Ausgangstreiber mit programmierbaren Treiberparametern
US5729158A (en) * 1995-07-07 1998-03-17 Sun Microsystems, Inc. Parametric tuning of an integrated circuit after fabrication
US5926651A (en) * 1995-07-28 1999-07-20 Intel Corporation Output buffer with current paths having different current carrying characteristics for providing programmable slew rate and signal strength
JPH0955651A (ja) * 1995-08-15 1997-02-25 Toshiba Corp 論理回路
US5742832A (en) * 1996-02-09 1998-04-21 Advanced Micro Devices Computer system with programmable driver output's strengths responsive to control signal matching preassigned address range
US5726583A (en) * 1996-07-19 1998-03-10 Kaplinsky; Cecil H. Programmable dynamic line-termination circuit
US5732027A (en) * 1996-12-30 1998-03-24 Cypress Semiconductor Corporation Memory having selectable output strength
US5959481A (en) 1997-02-18 1999-09-28 Rambus Inc. Bus driver circuit including a slew rate indicator circuit having a one shot circuit
WO1998036497A1 (en) * 1997-02-18 1998-08-20 Rambus, Inc. Bus driver circuit including a slew rate indicator circuit having a series of delay elements
SG68690A1 (en) * 1997-10-29 1999-11-16 Hewlett Packard Co Integrated circuit assembly having output pads with application specific characteristics and method of operation
US6046620A (en) * 1997-12-18 2000-04-04 Advanced Micro Devices, Inc. Programmable delay line
US6023176A (en) * 1998-03-27 2000-02-08 Cypress Semiconductor Corp. Input buffer
US6219813B1 (en) * 1998-06-29 2001-04-17 International Business Machines Corporation Programmable timing circuit for testing the cycle time of functional circuits on an integrated circuit chip
US6065127A (en) * 1998-09-14 2000-05-16 Globespan Semiconductor, Inc. Multi-mode buffer for digital signal processor
US6606705B1 (en) 1999-09-15 2003-08-12 Intel Corporation Method and apparatus for configuring an I/O buffer having an initialized default signaling level to operate at a sampled external circuit signaling level
US6300798B1 (en) * 1999-10-15 2001-10-09 Intel Corporation Method and apparatus for controlling compensated buffers
JP3463628B2 (ja) * 1999-10-18 2003-11-05 日本電気株式会社 スルーレート調整可能な出力回路を備えた半導体回路およびその調整方法ならびに自動調整装置
US6624662B1 (en) 2000-06-30 2003-09-23 Intel Corporation Buffer with compensating drive strength
CN100483424C (zh) * 2003-02-25 2009-04-29 Nxp股份有限公司 用于确定电源噪声的方法和电路布置
US7888962B1 (en) 2004-07-07 2011-02-15 Cypress Semiconductor Corporation Impedance matching circuit
US8036846B1 (en) 2005-10-20 2011-10-11 Cypress Semiconductor Corporation Variable impedance sense architecture and method
US7876133B1 (en) 2006-09-27 2011-01-25 Cypress Semiconductor Corporation Output buffer circuit
US7639037B1 (en) * 2008-06-27 2009-12-29 Sun Microsystems, Inc. Method and system for sizing flow control buffers
CN102460972B (zh) * 2009-06-30 2015-10-14 拉姆伯斯公司 用于调整时钟信号以补偿噪声的方法、系统和集成电路
US8985850B1 (en) * 2009-10-30 2015-03-24 Cypress Semiconductor Corporation Adaptive gate driver strength control
US8004329B1 (en) * 2010-03-19 2011-08-23 National Semiconductor Corporation Hardware performance monitor (HPM) with variable resolution for adaptive voltage scaling (AVS) systems
JP5682482B2 (ja) * 2011-07-05 2015-03-11 富士通セミコンダクター株式会社 スルーレートコントロール装置
US9343165B2 (en) 2012-12-31 2016-05-17 Sandisk Technologies Inc. Dynamic drive strength optimization
EP3386107B1 (de) 2017-04-03 2021-07-07 Nxp B.V. Datenverarbeitungsschaltungen

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US4291242A (en) * 1979-05-21 1981-09-22 Motorola, Inc. Driver circuit for use in an output buffer
US4639615A (en) * 1983-12-28 1987-01-27 At&T Bell Laboratories Trimmable loading elements to control clock skew
EP0253914A1 (de) * 1986-07-23 1988-01-27 Deutsche ITT Industries GmbH Isolierschicht-Feldeffekttransistor-Gegentakttreiberstufe mit Kompensierung von Betriebsparameterschwankungen und Fertigungsstreuungen
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
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EP0270296A3 (de) * 1986-12-01 1990-02-07 Fujitsu Limited Halbleiter-Logikschaltung
JPH0815210B2 (ja) * 1987-06-04 1996-02-14 日本電気株式会社 マスタスライス方式集積回路
JPS6467940A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Semiconductor integrated circuit
JPH07114348B2 (ja) * 1987-12-11 1995-12-06 日本電気株式会社 論理回路
US4816700A (en) * 1987-12-16 1989-03-28 Intel Corporation Two-phase non-overlapping clock generator
US5087842A (en) * 1988-01-06 1992-02-11 Digital Equipment Corporation Delay circuit having one of a plurality of delay lines which may be selected to provide an operation of a ring oscillator
JPH01251738A (ja) * 1988-03-31 1989-10-06 Toshiba Corp スタンダードセル
JPH07120225B2 (ja) * 1988-04-15 1995-12-20 富士通株式会社 半導体回路装置
JPH0229124A (ja) * 1988-07-19 1990-01-31 Toshiba Corp スタンダードセル
JPH0736422B2 (ja) * 1988-08-19 1995-04-19 株式会社東芝 クロック供給回路
US4988960A (en) * 1988-12-21 1991-01-29 Yamaha Corporation FM demodulation device and FM modulation device employing a CMOS signal delay device
US4965471A (en) * 1989-06-26 1990-10-23 Eastman Kodak Company BI-CMOS clock driver with reduced crossover current
US5093584A (en) * 1989-08-30 1992-03-03 International Business Machines Corporation Self calibrating timing circuit
US5001731A (en) * 1989-10-02 1991-03-19 Motorola, Inc. Method and apparatus for eliminating clockskew race condition errors
US5058132A (en) * 1989-10-26 1991-10-15 National Semiconductor Corporation Clock distribution system and technique
US5079440A (en) * 1990-03-15 1992-01-07 Intel Corporation Apparatus for generating computer clock pulses
US5077676A (en) * 1990-03-30 1991-12-31 International Business Machines Corporation Reducing clock skew in large-scale integrated circuits
US5073730A (en) * 1990-04-23 1991-12-17 International Business Machines Corporation Current transient reduction for vlsi chips
US5237224A (en) * 1990-10-11 1993-08-17 International Business Machines Corporation Variable self-correcting digital delay circuit
US5111086A (en) * 1990-11-19 1992-05-05 Wang Laboratories, Inc. Adjusting delay circuitry
US5231319A (en) * 1991-08-22 1993-07-27 Ncr Corporation Voltage variable delay circuit
US5245231A (en) * 1991-12-30 1993-09-14 Dell Usa, L.P. Integrated delay line
US5252867A (en) * 1992-02-14 1993-10-12 Vlsi Technology, Inc. Self-compensating digital delay semiconductor device with selectable output delays and method therefor

Also Published As

Publication number Publication date
JPH07326949A (ja) 1995-12-12
EP0611053A3 (de) 1997-08-13
US5444406A (en) 1995-08-22
EP0611053B1 (de) 2002-09-04
DE69431266D1 (de) 2002-10-10
EP0611053A2 (de) 1994-08-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition