DE602006009192D1 - Verfahren zur Herstellung von Dünnschichttransistoren mit Top-Gate-Geometrie - Google Patents

Verfahren zur Herstellung von Dünnschichttransistoren mit Top-Gate-Geometrie

Info

Publication number
DE602006009192D1
DE602006009192D1 DE602006009192T DE602006009192T DE602006009192D1 DE 602006009192 D1 DE602006009192 D1 DE 602006009192D1 DE 602006009192 T DE602006009192 T DE 602006009192T DE 602006009192 T DE602006009192 T DE 602006009192T DE 602006009192 D1 DE602006009192 D1 DE 602006009192D1
Authority
DE
Germany
Prior art keywords
thin
production
film transistors
gate geometry
geometry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006009192T
Other languages
English (en)
Inventor
William S Wong
Rene A Lujan
Eugene M Chow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xerox Corp
Original Assignee
Xerox Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xerox Corp filed Critical Xerox Corp
Publication of DE602006009192D1 publication Critical patent/DE602006009192D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
DE602006009192T 2005-07-28 2006-07-20 Verfahren zur Herstellung von Dünnschichttransistoren mit Top-Gate-Geometrie Active DE602006009192D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/193,847 US7344928B2 (en) 2005-07-28 2005-07-28 Patterned-print thin-film transistors with top gate geometry

Publications (1)

Publication Number Publication Date
DE602006009192D1 true DE602006009192D1 (de) 2009-10-29

Family

ID=37434035

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006009192T Active DE602006009192D1 (de) 2005-07-28 2006-07-20 Verfahren zur Herstellung von Dünnschichttransistoren mit Top-Gate-Geometrie

Country Status (4)

Country Link
US (3) US7344928B2 (de)
EP (1) EP1748477B1 (de)
JP (1) JP5296303B2 (de)
DE (1) DE602006009192D1 (de)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NZ542094A (en) * 2003-03-14 2008-12-24 Neose Technologies Inc Branched polymer conjugates comprising a peptide and water-soluble polymer chains
US7459400B2 (en) * 2005-07-18 2008-12-02 Palo Alto Research Center Incorporated Patterned structures fabricated by printing mask over lift-off pattern
US8114685B2 (en) * 2005-09-05 2012-02-14 Pioneer Corporation Method of manufacturing material to be etched
KR100829743B1 (ko) * 2005-12-09 2008-05-15 삼성에스디아이 주식회사 유기 박막 트랜지스터 및 이의 제조 방법, 이를 구비한평판 디스플레이 장치
US7524768B2 (en) * 2006-03-24 2009-04-28 Palo Alto Research Center Incorporated Method using monolayer etch masks in combination with printed masks
EP2005499B1 (de) * 2006-03-29 2013-04-24 Plastic Logic Limited Techniken zur bauelementeherstellung mit selbstausgerichteten elektroden
KR101272489B1 (ko) * 2006-10-03 2013-06-07 삼성디스플레이 주식회사 표시 기판, 이의 제조 방법 및 이를 구비하는 전기영동표시장치
US7696096B2 (en) * 2006-10-10 2010-04-13 Palo Alto Research Center Incorporated Self-aligned masks using multi-temperature phase-change materials
US20080296562A1 (en) * 2007-05-31 2008-12-04 Murduck James M Methods and apparatus for fabricating carbon nanotubes and carbon nanotube devices
WO2009037332A1 (en) * 2007-09-20 2009-03-26 Agfa-Gevaert N.V. Security laminates with interlaminated transparent embossed polymer hologram
EP2042576A1 (de) * 2007-09-20 2009-04-01 Agfa-Gevaert Sicherheitslaminat mit eingeprägtem transparentem Zwischenschicht-Polymerhologramm
JP2009094413A (ja) * 2007-10-11 2009-04-30 Sumitomo Chemical Co Ltd 薄膜能動素子、有機発光装置、表示装置、電子デバイスおよび薄膜能動素子の製造方法
CN105150656A (zh) * 2008-04-01 2015-12-16 爱克发-格法特公司 具有可通过触摸察觉的安全性特征的安全性层压板
WO2009121793A2 (en) * 2008-04-01 2009-10-08 Agfa Gevaert Lamination process for producung security laminates
WO2009121784A2 (en) * 2008-04-01 2009-10-08 Agfa Gevaert Security laminate having a security feature
TW200945596A (en) * 2008-04-16 2009-11-01 Mosel Vitelic Inc A method for making a solar cell with a selective emitter
KR20100023151A (ko) * 2008-08-21 2010-03-04 삼성모바일디스플레이주식회사 박막 트랜지스터 및 그 제조방법
EP2181858A1 (de) * 2008-11-04 2010-05-05 Agfa-Gevaert N.V. Sicherheitsdokument und Herstellungsverfahren
EP2199100A1 (de) * 2008-12-22 2010-06-23 Agfa-Gevaert N.V. Sicherheitslaminate für Sicherheitsdokumente
GB2466495B (en) * 2008-12-23 2013-09-04 Cambridge Display Tech Ltd Method of fabricating a self-aligned top-gate organic transistor
CN101894807B (zh) * 2009-05-22 2012-11-21 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
US8895352B2 (en) * 2009-06-02 2014-11-25 International Business Machines Corporation Method to improve nucleation of materials on graphene and carbon nanotubes
US8211782B2 (en) 2009-10-23 2012-07-03 Palo Alto Research Center Incorporated Printed material constrained by well structures
EP2332738B1 (de) 2009-12-10 2012-07-04 Agfa-Gevaert Sicherheitsdokument mit Sicherheitsmerkmal auf Rand
PL2335937T3 (pl) 2009-12-18 2013-06-28 Agfa Gevaert Znakowalna laserowo folia zabezpieczająca
PL2335938T3 (pl) 2009-12-18 2013-07-31 Agfa Gevaert Znakowalna laserowo folia zabezpieczająca
TW201304147A (zh) 2011-07-13 2013-01-16 Chunghwa Picture Tubes Ltd 薄膜電晶體及其製造方法
GB201112548D0 (en) * 2011-07-21 2011-08-31 Cambridge Display Tech Ltd Method of forming a top-gate transistor
US8569121B2 (en) * 2011-11-01 2013-10-29 International Business Machines Corporation Graphene and nanotube/nanowire transistor with a self-aligned gate structure on transparent substrates and method of making same
WO2015076334A1 (ja) * 2013-11-21 2015-05-28 株式会社ニコン トランジスタの製造方法およびトランジスタ
KR20200008630A (ko) 2017-05-24 2020-01-28 더 트러스티스 오브 콜롬비아 유니버시티 인 더 시티 오브 뉴욕 분산 설계된 유전성 메타표면에 의한 광대역 수색성의 평평한 광학 부품
US20190025463A1 (en) * 2017-07-19 2019-01-24 President And Fellows Of Harvard College Substrate-formed metasurface devices
CN107678247B (zh) * 2017-08-25 2020-05-29 长安大学 一种硅基集成曝光量测量器件
EP3676973A4 (de) 2017-08-31 2021-05-05 Metalenz, Inc. Integration von linse mit durchlässiger metaoberfläche
US10566352B2 (en) * 2017-12-07 2020-02-18 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Array substrate and manufacturing method thereof
US11217700B2 (en) * 2018-12-07 2022-01-04 Cornell University Micron scale tin oxide-based semiconductor devices
US11927769B2 (en) 2022-03-31 2024-03-12 Metalenz, Inc. Polarization sorting metasurface microlens array device

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3958252A (en) 1971-11-12 1976-05-18 Casio Computer Co., Ltd. Ink jet type character recording apparatus
US4131899A (en) 1977-02-22 1978-12-26 Burroughs Corporation Droplet generator for an ink jet printer
JPS6178166A (ja) * 1984-09-25 1986-04-21 Matsushita Electric Ind Co Ltd 薄膜トランジスタ−アレ−とその製造方法
JPS6230376A (ja) * 1985-07-31 1987-02-09 Fujitsu Ltd 薄膜トランジスタの製造方法
JPH0622245B2 (ja) 1986-05-02 1994-03-23 富士ゼロックス株式会社 薄膜トランジスタの製造方法
US4945067A (en) * 1988-09-16 1990-07-31 Xerox Corporation Intra-gate offset high voltage thin film transistor with misalignment immunity and method of its fabrication
US4959674A (en) 1989-10-03 1990-09-25 Xerox Corporation Acoustic ink printhead having reflection coating for improved ink drop ejection control
FR2675947A1 (fr) * 1991-04-23 1992-10-30 France Telecom Procede de passivation locale d'un substrat par une couche de carbone amorphe hydrogene et procede de fabrication de transistors en couches minces sur ce substrat passive.
JP3735885B2 (ja) 1995-04-27 2006-01-18 ソニー株式会社 プリンタ装置
US5733804A (en) 1995-12-22 1998-03-31 Xerox Corporation Fabricating fully self-aligned amorphous silicon device
KR100243297B1 (ko) * 1997-07-28 2000-02-01 윤종용 다결정실리콘 박막 트랜지스터-액정표시장치 및그 제조방법
KR100306801B1 (ko) * 1998-06-25 2002-05-13 박종섭 박막트랜지스터및그의제조방법
US6116718A (en) 1998-09-30 2000-09-12 Xerox Corporation Print head for use in a ballistic aerosol marking apparatus
GB9907019D0 (en) * 1999-03-27 1999-05-19 Koninkl Philips Electronics Nv Thin film transistors and their manufacture
GB9919913D0 (en) * 1999-08-24 1999-10-27 Koninkl Philips Electronics Nv Thin-film transistors and method for producing the same
TW437097B (en) * 1999-12-20 2001-05-28 Hannstar Display Corp Manufacturing method for thin film transistor
US6872320B2 (en) 2001-04-19 2005-03-29 Xerox Corporation Method for printing etch masks using phase-change materials
US6742884B2 (en) 2001-04-19 2004-06-01 Xerox Corporation Apparatus for printing etch masks using phase-change materials
US6972261B2 (en) * 2002-06-27 2005-12-06 Xerox Corporation Method for fabricating fine features by jet-printing and surface treatment
US7309563B2 (en) 2003-12-19 2007-12-18 Palo Alto Research Center Incorporated Patterning using wax printing and lift off
US7459400B2 (en) * 2005-07-18 2008-12-02 Palo Alto Research Center Incorporated Patterned structures fabricated by printing mask over lift-off pattern

Also Published As

Publication number Publication date
US20070026585A1 (en) 2007-02-01
US20100252927A1 (en) 2010-10-07
EP1748477B1 (de) 2009-09-16
US7344928B2 (en) 2008-03-18
US7884361B2 (en) 2011-02-08
JP5296303B2 (ja) 2013-09-25
EP1748477A2 (de) 2007-01-31
US20080121884A1 (en) 2008-05-29
EP1748477A3 (de) 2008-02-20
JP2007036247A (ja) 2007-02-08
US7804090B2 (en) 2010-09-28

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