DE602006006595D1 - Halbleiterspeichervorrichtung und elektronisches Gerät - Google Patents

Halbleiterspeichervorrichtung und elektronisches Gerät

Info

Publication number
DE602006006595D1
DE602006006595D1 DE602006006595T DE602006006595T DE602006006595D1 DE 602006006595 D1 DE602006006595 D1 DE 602006006595D1 DE 602006006595 T DE602006006595 T DE 602006006595T DE 602006006595 T DE602006006595 T DE 602006006595T DE 602006006595 D1 DE602006006595 D1 DE 602006006595D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
electronic device
memory device
electronic
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006006595T
Other languages
English (en)
Inventor
Yasunori Koide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of DE602006006595D1 publication Critical patent/DE602006006595D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
DE602006006595T 2005-10-06 2006-09-14 Halbleiterspeichervorrichtung und elektronisches Gerät Active DE602006006595D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005294123A JP4840720B2 (ja) 2005-10-06 2005-10-06 半導体記憶装置および電子機器

Publications (1)

Publication Number Publication Date
DE602006006595D1 true DE602006006595D1 (de) 2009-06-10

Family

ID=37671000

Family Applications (2)

Application Number Title Priority Date Filing Date
DE602006006517T Active DE602006006517D1 (de) 2005-10-06 2006-09-14 Halbleiterspeichervorrichtung und elektronisches Gerät
DE602006006595T Active DE602006006595D1 (de) 2005-10-06 2006-09-14 Halbleiterspeichervorrichtung und elektronisches Gerät

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE602006006517T Active DE602006006517D1 (de) 2005-10-06 2006-09-14 Halbleiterspeichervorrichtung und elektronisches Gerät

Country Status (7)

Country Link
US (2) US7463505B2 (de)
EP (2) EP1959453B1 (de)
JP (1) JP4840720B2 (de)
KR (1) KR100734984B1 (de)
CN (1) CN1945735B (de)
DE (2) DE602006006517D1 (de)
TW (1) TW200729204A (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2015362A1 (de) * 2007-06-04 2009-01-14 STMicroelectronics (Crolles 2) SAS Halbleitermatrix und deren Herstellungsverfahren
JP5452911B2 (ja) * 2008-12-19 2014-03-26 ローム株式会社 半導体装置
US9972374B1 (en) * 2016-10-30 2018-05-15 AUCMOS Technologies USA, Inc. Ferroelectric random access memory (FeRAM) array with segmented plate lines that are electrically-isolated from each other
US10418085B2 (en) * 2017-07-20 2019-09-17 Micron Technology, Inc. Memory plate segmentation to reduce operating power
US10818334B2 (en) * 2018-06-26 2020-10-27 AUCMOS Technologies USA, Inc. Ferroelectric memory array with variable plate-line architecture
US11282849B2 (en) 2019-09-03 2022-03-22 Yangtze Memory Technologies Co., Ltd. Non-volatile memory device utilizing dummy memory block as pool capacitor
CN110741473B (zh) * 2019-09-03 2021-04-16 长江存储科技有限责任公司 利用虚设存储块作为池电容器的非易失性存储器件
CN113113385A (zh) * 2021-04-12 2021-07-13 无锡拍字节科技有限公司 用于半导体器件的信号线结构以及布线方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5107459A (en) * 1990-04-20 1992-04-21 International Business Machines Corporation Stacked bit-line architecture for high density cross-point memory cell array
US6028783A (en) * 1997-11-14 2000-02-22 Ramtron International Corporation Memory cell configuration for a 1T/1C ferroelectric memory
US6370057B1 (en) * 1999-02-24 2002-04-09 Kabushiki Kaisha Toshiba Semiconductor memory device having plate lines and precharge circuits
KR19990085673A (ko) * 1998-05-20 1999-12-15 윤종용 트위스트된 비트라인 구조를 갖는 반도체 메모리 장치
US6249451B1 (en) 1999-02-08 2001-06-19 Kabushiki Kaisha Toshiba Data line connections with twisting scheme technical field
US6252814B1 (en) * 1999-04-29 2001-06-26 International Business Machines Corp. Dummy wordline circuitry
US6172925B1 (en) * 1999-06-14 2001-01-09 Transmeta Corporation Memory array bitline timing circuit
JP2002083493A (ja) * 2000-09-05 2002-03-22 Toshiba Corp 半導体記憶装置
JP4329919B2 (ja) * 2001-03-13 2009-09-09 Ｏｋｉセミコンダクタ株式会社 半導体メモリおよび半導体メモリの駆動方法
KR100447228B1 (ko) * 2001-11-05 2004-09-04 주식회사 하이닉스반도체 불휘발성 강유전체 메모리 셀 어레이 및 그 구동장치
JP2003263886A (ja) 2002-03-08 2003-09-19 Fujitsu Ltd ビット線容量を最適化できる強誘電体メモリ
KR100437452B1 (ko) * 2002-04-17 2004-06-23 삼성전자주식회사 상변환 기억 셀들 및 그 제조방법들
US6873536B2 (en) * 2002-04-19 2005-03-29 Texas Instruments Incorporated Shared data buffer in FeRAM utilizing word line direction segmentation
JP4646485B2 (ja) * 2002-06-25 2011-03-09 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
JP4225749B2 (ja) * 2002-08-07 2009-02-18 株式会社ルネサステクノロジ 半導体記憶装置
US6649945B1 (en) * 2002-10-18 2003-11-18 Kabushiki Kaisha Toshiba Wiring layout to weaken an electric field generated between the lines exposed to a high voltage
JP3597185B2 (ja) * 2002-11-12 2004-12-02 沖電気工業株式会社 強誘電体メモリ
JP4696462B2 (ja) 2004-04-01 2011-06-08 トヨタ自動車株式会社 膜電極接合体の製造方法

Also Published As

Publication number Publication date
CN1945735B (zh) 2010-10-06
KR100734984B1 (ko) 2007-07-06
US20090059649A1 (en) 2009-03-05
EP1772872A1 (de) 2007-04-11
EP1959453A1 (de) 2008-08-20
JP2007103805A (ja) 2007-04-19
KR20070038877A (ko) 2007-04-11
TW200729204A (en) 2007-08-01
EP1772872B1 (de) 2009-04-29
US20070081374A1 (en) 2007-04-12
CN1945735A (zh) 2007-04-11
US7995370B2 (en) 2011-08-09
US7463505B2 (en) 2008-12-09
EP1959453B1 (de) 2009-04-29
DE602006006517D1 (de) 2009-06-10
JP4840720B2 (ja) 2011-12-21

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Legal Events

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