DE602004016579D1 - Integrierte schaltung und verfahren zum prüfen einer integrierten schaltung mit mehreren abgriffen - Google Patents

Integrierte schaltung und verfahren zum prüfen einer integrierten schaltung mit mehreren abgriffen

Info

Publication number
DE602004016579D1
DE602004016579D1 DE602004016579T DE602004016579T DE602004016579D1 DE 602004016579 D1 DE602004016579 D1 DE 602004016579D1 DE 602004016579 T DE602004016579 T DE 602004016579T DE 602004016579 T DE602004016579 T DE 602004016579T DE 602004016579 D1 DE602004016579 D1 DE 602004016579D1
Authority
DE
Germany
Prior art keywords
test
integrated circuit
test path
path
bypass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004016579T
Other languages
English (en)
Inventor
Yossi Amon
Dimitri Akselrod
Eyal Segev
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of DE602004016579D1 publication Critical patent/DE602004016579D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE602004016579T 2004-11-22 2004-11-22 Integrierte schaltung und verfahren zum prüfen einer integrierten schaltung mit mehreren abgriffen Active DE602004016579D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2004/014805 WO2006053587A1 (en) 2004-11-22 2004-11-22 Integrated circuit and a method for testing a multi-tap integrated circuit

Publications (1)

Publication Number Publication Date
DE602004016579D1 true DE602004016579D1 (de) 2008-10-23

Family

ID=34961738

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004016579T Active DE602004016579D1 (de) 2004-11-22 2004-11-22 Integrierte schaltung und verfahren zum prüfen einer integrierten schaltung mit mehreren abgriffen

Country Status (8)

Country Link
US (1) US8754668B2 (de)
EP (1) EP1817596B1 (de)
JP (1) JP2008520980A (de)
CN (1) CN101065679B (de)
AT (1) ATE408153T1 (de)
DE (1) DE602004016579D1 (de)
TW (1) TW200632347A (de)
WO (1) WO2006053587A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8572433B2 (en) * 2010-03-10 2013-10-29 Texas Instruments Incorporated JTAG IC with commandable circuit controlling data register control router
US9110142B2 (en) * 2011-09-30 2015-08-18 Freescale Semiconductor, Inc. Methods and apparatus for testing multiple-IC devices
US8914693B2 (en) * 2012-02-15 2014-12-16 International Business Machines Corporation Apparatus for JTAG-driven remote scanning
CN103383543B (zh) * 2012-05-02 2017-08-15 飞思卡尔半导体公司 片上系统及其控制模块
EP2748622B1 (de) * 2012-05-10 2016-08-10 Telefonaktiebolaget LM Ericsson (publ) Verfahren zum testen eines multichipsystems oder eines einzelchips und system dafür
US9810739B2 (en) * 2015-10-27 2017-11-07 Andes Technology Corporation Electronic system, system diagnostic circuit and operation method thereof
CN105388881B (zh) * 2015-11-04 2017-10-20 北京长城华冠汽车科技股份有限公司 一种整车控制器的故障检测显示装置和方法
CN105425766B (zh) * 2015-11-04 2017-10-20 北京长城华冠汽车科技股份有限公司 一种整车控制器的故障检测装置和方法
US10473711B2 (en) * 2016-04-15 2019-11-12 Infineon Technologies Ag Multi-channel fault detection with a single diagnosis output
CN112131174A (zh) * 2019-06-25 2020-12-25 北京百度网讯科技有限公司 支持在多个芯片之间通信的方法、装置、电子设备和计算机存储介质
CN112445663B (zh) * 2019-09-02 2022-05-03 瑞昱半导体股份有限公司 测试存取端口电路
CN112098818B (zh) * 2020-11-02 2021-02-02 创意电子(南京)有限公司 一种基于标准边界扫描电路的sip器件测试系统

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0419734B1 (de) * 1989-08-25 1995-06-14 Koninklijke Philips Electronics N.V. Verfahren zum Testen von hierarchisch organisierten integrierten Schaltungen und integrierte Schaltungen, geeignet für einen solchen Test
JP2676169B2 (ja) * 1989-12-27 1997-11-12 三菱電機株式会社 スキャンパス回路
US5377198A (en) * 1991-11-27 1994-12-27 Ncr Corporation (Nka At&T Global Information Solutions Company JTAG instruction error detection
EP0826974B1 (de) 1996-08-30 2005-10-19 Texas Instruments Incorporated Vorrichtung zur Prüfung von integrierten Schaltungen
JPH11326460A (ja) * 1998-05-21 1999-11-26 Nec Eng Ltd バウンダリスキャン回路
US6314539B1 (en) * 1998-10-21 2001-11-06 Xilinx, Inc. Boundary-scan register cell with bypass circuit
JP2003035751A (ja) * 2001-07-25 2003-02-07 Mitsubishi Electric Corp 半導体集積回路の試験装置及び試験方法
KR100448706B1 (ko) * 2002-07-23 2004-09-13 삼성전자주식회사 단일 칩 시스템 및 이 시스템의 테스트/디버그 방법
JP4274806B2 (ja) 2003-01-28 2009-06-10 株式会社リコー 半導体集積回路およびスキャンテスト法

Also Published As

Publication number Publication date
WO2006053587A1 (en) 2006-05-26
US8754668B2 (en) 2014-06-17
CN101065679B (zh) 2010-09-01
JP2008520980A (ja) 2008-06-19
US20100019794A1 (en) 2010-01-28
ATE408153T1 (de) 2008-09-15
EP1817596A1 (de) 2007-08-15
TW200632347A (en) 2006-09-16
EP1817596B1 (de) 2008-09-10
CN101065679A (zh) 2007-10-31

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