DE602004014459D1 - Halbleiterspeicher mit synchronen/asynchronen -Modus-Auswahl während der Abschaltung - Google Patents

Halbleiterspeicher mit synchronen/asynchronen -Modus-Auswahl während der Abschaltung

Info

Publication number
DE602004014459D1
DE602004014459D1 DE602004014459T DE602004014459T DE602004014459D1 DE 602004014459 D1 DE602004014459 D1 DE 602004014459D1 DE 602004014459 T DE602004014459 T DE 602004014459T DE 602004014459 T DE602004014459 T DE 602004014459T DE 602004014459 D1 DE602004014459 D1 DE 602004014459D1
Authority
DE
Germany
Prior art keywords
synchronous
semiconductor memory
mode selection
asynchronous mode
during shutdown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004014459T
Other languages
English (en)
Inventor
Toru Koga
Tomohiro Kawakubo
Tatsuya Kanda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE602004014459D1 publication Critical patent/DE602004014459D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
DE602004014459T 2003-11-06 2004-06-23 Halbleiterspeicher mit synchronen/asynchronen -Modus-Auswahl während der Abschaltung Expired - Lifetime DE602004014459D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003376736A JP4386706B2 (ja) 2003-11-06 2003-11-06 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE602004014459D1 true DE602004014459D1 (de) 2008-07-31

Family

ID=33562818

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004014459T Expired - Lifetime DE602004014459D1 (de) 2003-11-06 2004-06-23 Halbleiterspeicher mit synchronen/asynchronen -Modus-Auswahl während der Abschaltung

Country Status (5)

Country Link
US (1) US6845055B1 (de)
EP (1) EP1530219B1 (de)
JP (1) JP4386706B2 (de)
CN (1) CN100429723C (de)
DE (1) DE602004014459D1 (de)

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US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US7590796B2 (en) * 2006-07-31 2009-09-15 Metaram, Inc. System and method for power management in memory systems
US8077535B2 (en) * 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8041881B2 (en) * 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8327104B2 (en) * 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US9542352B2 (en) * 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US20080126690A1 (en) * 2006-02-09 2008-05-29 Rajan Suresh N Memory module with memory stack
US7392338B2 (en) * 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8359187B2 (en) * 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US7580312B2 (en) * 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
US7472220B2 (en) * 2006-07-31 2008-12-30 Metaram, Inc. Interface circuit system and method for performing power management operations utilizing power management signals
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US7609567B2 (en) * 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US7386656B2 (en) * 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
GB2441726B (en) * 2005-06-24 2010-08-11 Metaram Inc An integrated memory core and memory interface circuit
US8090897B2 (en) * 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
JP5242397B2 (ja) * 2005-09-02 2013-07-24 メタラム インコーポレイテッド Ｄｒａｍをスタックする方法及び装置
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
JP4267006B2 (ja) * 2006-07-24 2009-05-27 エルピーダメモリ株式会社 半導体記憶装置
US20080025136A1 (en) * 2006-07-31 2008-01-31 Metaram, Inc. System and method for storing at least a portion of information received in association with a first operation for use in performing a second operation
US20080028137A1 (en) * 2006-07-31 2008-01-31 Schakel Keith R Method and Apparatus For Refresh Management of Memory Modules
US20080028135A1 (en) * 2006-07-31 2008-01-31 Metaram, Inc. Multiple-component memory interface system and method
US7724589B2 (en) * 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8209479B2 (en) * 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US7983099B2 (en) 2007-12-20 2011-07-19 Mosaid Technologies Incorporated Dual function compatible non-volatile memory device
EP2223301A4 (de) * 2007-12-21 2012-04-04 Mosaid Technologies Inc Nichtflüchtige halbleiterspeicheranordnung mit stromsparmerkmal
JP4759717B2 (ja) * 2008-02-18 2011-08-31 スパンション エルエルシー 同期型不揮発性メモリおよびメモリシステム
WO2010144624A1 (en) * 2009-06-09 2010-12-16 Google Inc. Programming of dimm termination resistance values
US8942056B2 (en) 2011-02-23 2015-01-27 Rambus Inc. Protocol for memory power-mode control
US8804449B2 (en) 2012-09-06 2014-08-12 Micron Technology, Inc. Apparatus and methods to provide power management for memory devices
DE102014113239B4 (de) 2014-09-15 2021-02-25 Dr. Ing. H.C. F. Porsche Aktiengesellschaft Bügel für eine Rohbaustruktur eines Kraftfahrzeugs
CN105355229A (zh) * 2015-10-29 2016-02-24 同济大学 异步电路系统对同步随机存储器的写入电路和读取电路
KR20220055741A (ko) * 2020-10-27 2022-05-04 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그의 동작 방법

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JP3790021B2 (ja) * 1997-08-13 2006-06-28 株式会社東芝 半導体記憶装置
JP4060442B2 (ja) * 1998-05-28 2008-03-12 富士通株式会社 メモリデバイス
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Also Published As

Publication number Publication date
US6845055B1 (en) 2005-01-18
CN1614716A (zh) 2005-05-11
JP2005141828A (ja) 2005-06-02
JP4386706B2 (ja) 2009-12-16
CN100429723C (zh) 2008-10-29
EP1530219B1 (de) 2008-06-18
EP1530219A2 (de) 2005-05-11
EP1530219A3 (de) 2006-01-18

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE