DE602004012492D1 - DMA-Steuerung mit Busbesetzungszeit-Beschränkung sowie DMA-Parametersätze für mehrere logische Prozessoren - Google Patents

DMA-Steuerung mit Busbesetzungszeit-Beschränkung sowie DMA-Parametersätze für mehrere logische Prozessoren

Info

Publication number
DE602004012492D1
DE602004012492D1 DE602004012492T DE602004012492T DE602004012492D1 DE 602004012492 D1 DE602004012492 D1 DE 602004012492D1 DE 602004012492 T DE602004012492 T DE 602004012492T DE 602004012492 T DE602004012492 T DE 602004012492T DE 602004012492 D1 DE602004012492 D1 DE 602004012492D1
Authority
DE
Germany
Prior art keywords
dma
well
parameter sets
time restriction
logical processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE602004012492T
Other languages
English (en)
Other versions
DE602004012492T2 (de
Inventor
Akihiro Furuta
Nobuo Higaki
Tetsuya Tanaka
Tsuneyuki Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE602004012492D1 publication Critical patent/DE602004012492D1/de
Application granted granted Critical
Publication of DE602004012492T2 publication Critical patent/DE602004012492T2/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
DE602004012492T 2003-08-01 2004-07-29 DMA-Steuerung mit Busbesetzungszeit-Beschränkung sowie DMA-Parametersätze für mehrere logische Prozessoren Expired - Fee Related DE602004012492T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003285080 2003-08-01
JP2003285080A JP2005056067A (ja) 2003-08-01 2003-08-01 Ｄｍａ転送制御装置

Publications (2)

Publication Number Publication Date
DE602004012492D1 true DE602004012492D1 (de) 2008-04-30
DE602004012492T2 DE602004012492T2 (de) 2009-04-09

Family

ID=33535731

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004012492T Expired - Fee Related DE602004012492T2 (de) 2003-08-01 2004-07-29 DMA-Steuerung mit Busbesetzungszeit-Beschränkung sowie DMA-Parametersätze für mehrere logische Prozessoren

Country Status (5)

Country Link
US (1) US7305499B2 (de)
EP (1) EP1503292B1 (de)
JP (1) JP2005056067A (de)
CN (1) CN100388253C (de)
DE (1) DE602004012492T2 (de)

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US7734832B2 (en) * 2004-11-10 2010-06-08 Microsoft Corporation Method and system for structured programmed input/output transactions
US8079036B2 (en) * 2004-11-10 2011-12-13 Microsoft Corporation Method and system for structured DMA transactions
JP2006157580A (ja) * 2004-11-30 2006-06-15 Ricoh Co Ltd 画像処理装置、画像形成装置、画像処理方法、コンピュータプログラム及び記録媒体
JP2006178787A (ja) * 2004-12-22 2006-07-06 Toshiba Corp 半導体装置とそのデータ転送方法
CN100369024C (zh) * 2005-01-17 2008-02-13 北京中星微电子有限公司 直接存储访问控制装置和图像处理系统以及传输方法
US7546391B2 (en) * 2005-05-13 2009-06-09 Texas Instruments Incorporated Direct memory access channel controller with quick channels, event queue and active channel memory protection
US7555577B2 (en) * 2005-05-13 2009-06-30 Texas Instruments Incorporated Data transfer apparatus with channel controller and transfer controller capable of slave and standalone operation
JP2006338353A (ja) * 2005-06-02 2006-12-14 Sony Corp 情報処理装置および情報処理方法、並びにプログラム
US8001430B2 (en) 2005-06-30 2011-08-16 Freescale Semiconductor, Inc. Device and method for controlling an execution of a DMA task
DE602005015632D1 (de) * 2005-06-30 2009-09-03 Freescale Semiconductor Inc Einrichtung und verfahren zur steuerung mehrerer dma-tasks
WO2007003984A1 (en) 2005-06-30 2007-01-11 Freescale Semiconductor, Inc. Device and method for arbitrating between direct memory access task requests
JP2008216472A (ja) * 2007-03-01 2008-09-18 Matsushita Electric Ind Co Ltd 音声復号化装置及び音声復号化システム
JP4972692B2 (ja) * 2007-08-30 2012-07-11 パナソニック株式会社 Ｄｍａ制御装置およびデータ転送方法
US20090063725A1 (en) * 2007-08-31 2009-03-05 O2Micro Inc. Direct memory access system
US8266337B2 (en) * 2007-12-06 2012-09-11 International Business Machines Corporation Dynamic logical data channel assignment using channel bitmap
JP2011060066A (ja) 2009-09-11 2011-03-24 Renesas Electronics Corp データ処理回路
US8996913B2 (en) 2010-07-27 2015-03-31 Panasonic Intellectual Property Management Co., Ltd. Data transfer control device and data transfer control method
JP5644531B2 (ja) * 2011-01-19 2014-12-24 富士通セミコンダクター株式会社 データ転送装置及びデータ転送方法
EP2652589A1 (de) * 2011-06-24 2013-10-23 Hitachi, Ltd. Speichersystem
US8447897B2 (en) * 2011-06-24 2013-05-21 Freescale Semiconductor, Inc. Bandwidth control for a direct memory access unit within a data processing system
JP5803689B2 (ja) * 2012-01-17 2015-11-04 トヨタ自動車株式会社 情報処理装置およびｄｍａコントローラの動作確認方法
US9128925B2 (en) 2012-04-24 2015-09-08 Freescale Semiconductor, Inc. System and method for direct memory access buffer utilization by setting DMA controller with plurality of arbitration weights associated with different DMA engines
JP2014010759A (ja) * 2012-07-02 2014-01-20 Toshiba Corp ブリッジ装置およびその方法、ストレージ装置、ならびにプログラム
JP6004057B2 (ja) * 2015-07-09 2016-10-05 トヨタ自動車株式会社 情報処理装置およびｄｍａコントローラの動作確認方法
FR3057969B1 (fr) * 2016-10-25 2019-11-01 Thales Systeme de pilotage deterministe du fonctionnement de moyens de transfert de donnees par acces direct a des moyens de memorisation
CN114661644B (zh) * 2022-02-17 2024-04-09 之江实验室 辅助3d架构近存计算加速器系统的预存储dma装置

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JPH05250305A (ja) * 1992-03-06 1993-09-28 Mitsubishi Electric Corp データ転送制御方式
US5680556A (en) * 1993-11-12 1997-10-21 International Business Machines Corporation Computer system and method of operation thereof wherein a BIOS ROM can be selectively locatable on diffeent buses
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US5603050A (en) * 1995-03-03 1997-02-11 Compaq Computer Corporation Direct memory access controller having programmable timing
JPH09223102A (ja) 1995-12-14 1997-08-26 Ricoh Co Ltd ダイレクトメモリアクセスコントローラ
JP3712842B2 (ja) * 1997-08-05 2005-11-02 株式会社リコー データ転送制御方法、データ転送制御装置及び情報記録媒体
US6363445B1 (en) * 1998-10-15 2002-03-26 Micron Technology, Inc. Method of bus arbitration using requesting device bandwidth and priority ranking
JP2000132505A (ja) 1998-10-27 2000-05-12 Matsushita Electric Ind Co Ltd バスアクセス方法および装置とその利用装置およびシステム
JP3258300B2 (ja) 1999-09-03 2002-02-18 松下電器産業株式会社 Ｄｍａ転送装置および画像復号装置
US6542940B1 (en) * 1999-10-25 2003-04-01 Motorola, Inc. Method and apparatus for controlling task execution in a direct memory access controller
JP2002041445A (ja) 2000-05-19 2002-02-08 Matsushita Electric Ind Co Ltd 高性能ｄｍａコントローラ
EP1193610B1 (de) * 2000-09-29 2006-11-15 Ricoh Company, Ltd. Datenverarbeitungsvorrichtung und DMA-Datenübertragungsverfahren
JP2002163239A (ja) * 2000-11-22 2002-06-07 Toshiba Corp マルチプロセッサシステムおよびその制御方法
KR100367084B1 (ko) * 2000-12-22 2003-01-09 한국전자통신연구원 실시간 고속의 데이터 처리용 디엠에이 제어기 및 제어방법
KR100456696B1 (ko) * 2002-05-21 2004-11-10 삼성전자주식회사 집적회로장치의 버스중재기

Also Published As

Publication number Publication date
US20050050241A1 (en) 2005-03-03
US7305499B2 (en) 2007-12-04
EP1503292B1 (de) 2008-03-19
DE602004012492T2 (de) 2009-04-09
JP2005056067A (ja) 2005-03-03
CN1591374A (zh) 2005-03-09
EP1503292A2 (de) 2005-02-02
CN100388253C (zh) 2008-05-14
EP1503292A3 (de) 2005-03-23

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP

8339 Ceased/non-payment of the annual fee