DE602005027790D1 - Bussteuerung - Google Patents

Bussteuerung

Info

Publication number
DE602005027790D1
DE602005027790D1 DE602005027790T DE602005027790T DE602005027790D1 DE 602005027790 D1 DE602005027790 D1 DE 602005027790D1 DE 602005027790 T DE602005027790 T DE 602005027790T DE 602005027790 T DE602005027790 T DE 602005027790T DE 602005027790 D1 DE602005027790 D1 DE 602005027790D1
Authority
DE
Germany
Prior art keywords
bus control
bus
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005027790T
Other languages
English (en)
Inventor
Yuzuru Tanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Japan Ltd
Original Assignee
Texas Instruments Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Japan Ltd filed Critical Texas Instruments Japan Ltd
Publication of DE602005027790D1 publication Critical patent/DE602005027790D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
DE602005027790T 2004-10-27 2005-10-27 Bussteuerung Active DE602005027790D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004312310A JP4260720B2 (ja) 2004-10-27 2004-10-27 バス制御装置

Publications (1)

Publication Number Publication Date
DE602005027790D1 true DE602005027790D1 (de) 2011-06-16

Family

ID=35457122

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005027790T Active DE602005027790D1 (de) 2004-10-27 2005-10-27 Bussteuerung

Country Status (4)

Country Link
US (1) US7581049B2 (de)
EP (1) EP1653370B1 (de)
JP (1) JP4260720B2 (de)
DE (1) DE602005027790D1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4233373B2 (ja) * 2003-04-14 2009-03-04 株式会社ルネサステクノロジ データ転送制御装置
KR100706801B1 (ko) * 2006-01-04 2007-04-12 삼성전자주식회사 멀티 프로세서 시스템 및 그것의 데이터 전송 방법
JP4874065B2 (ja) * 2006-11-22 2012-02-08 ルネサスエレクトロニクス株式会社 バス中継装置及びシステム
US7865644B2 (en) * 2007-10-30 2011-01-04 International Business Machines Corporation Method and apparatus for attaching multiple slave devices to a single bus controller interface while supporting command pipelining
JP5127470B2 (ja) * 2008-01-15 2013-01-23 三菱電機株式会社 バス装置
JP5440419B2 (ja) * 2010-06-29 2014-03-12 富士通セミコンダクター株式会社 情報処理システム
US8433838B2 (en) * 2010-09-17 2013-04-30 International Business Machines Corporation Remote multiplexing devices on a serial peripheral interface bus
US8516167B2 (en) * 2011-08-03 2013-08-20 Atmel Corporation Microcontroller system bus scheduling for multiport slave modules
JP2013122713A (ja) * 2011-12-12 2013-06-20 Toshiba Corp 半導体装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710891A (en) * 1995-03-31 1998-01-20 Sun Microsystems, Inc. Pipelined distributed bus arbitration system
EP0752666A3 (de) * 1995-07-06 2004-04-28 Sun Microsystems, Inc. Verfahren und Vorrichtung zur Beschleunigung von Sklave-Anforderungen in einem paketvermittelten Computersystem
JPH103447A (ja) * 1996-06-18 1998-01-06 Matsushita Electric Ind Co Ltd バスブリッジ装置
US6275890B1 (en) * 1998-08-19 2001-08-14 International Business Machines Corporation Low latency data path in a cross-bar switch providing dynamically prioritized bus arbitration
US6788703B2 (en) * 1998-12-30 2004-09-07 Nortel Networks Limited DS0 on ATM, mapping and handling
JP3444247B2 (ja) * 1999-09-29 2003-09-08 日本電気株式会社 パケット速度変換器
US6587905B1 (en) * 2000-06-29 2003-07-01 International Business Machines Corporation Dynamic data bus allocation
US6823411B2 (en) * 2002-01-30 2004-11-23 International Business Machines Corporation N-way psuedo cross-bar having an arbitration feature using discrete processor local busses
TWI223155B (en) * 2002-10-04 2004-11-01 Leadtek Research Inc Integrated peripheral component interconnection interface and bus system
US7802049B2 (en) * 2002-10-30 2010-09-21 Intel Corporation Links having flexible lane allocation
GB2402761B (en) * 2003-06-12 2006-02-22 Advanced Risc Mach Ltd Improvements in flexibility of a bus interconnect block for a data processing apparatus
US6954821B2 (en) * 2003-07-31 2005-10-11 Freescale Semiconductor, Inc. Crossbar switch that supports a multi-port slave device and method of operation

Also Published As

Publication number Publication date
EP1653370A2 (de) 2006-05-03
EP1653370B1 (de) 2011-05-04
US7581049B2 (en) 2009-08-25
EP1653370A3 (de) 2007-04-25
JP2006127022A (ja) 2006-05-18
JP4260720B2 (ja) 2009-04-30
US20060090024A1 (en) 2006-04-27

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