DE60135290D1 - Sequenzschaltung und Halbleiteranordnung unter Verwendung einer solchen - Google Patents

Sequenzschaltung und Halbleiteranordnung unter Verwendung einer solchen

Info

Publication number
DE60135290D1
DE60135290D1 DE60135290T DE60135290T DE60135290D1 DE 60135290 D1 DE60135290 D1 DE 60135290D1 DE 60135290 T DE60135290 T DE 60135290T DE 60135290 T DE60135290 T DE 60135290T DE 60135290 D1 DE60135290 D1 DE 60135290D1
Authority
DE
Germany
Prior art keywords
semiconductor device
sequence circuit
sequence
circuit
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60135290T
Other languages
English (en)
Inventor
Atsushi Takeuchi
Masaharu Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Fujitsu Semiconductor Ltd
Original Assignee
Toshiba Corp
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Fujitsu Ltd filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE60135290D1 publication Critical patent/DE60135290D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
DE60135290T 2000-11-06 2001-10-26 Sequenzschaltung und Halbleiteranordnung unter Verwendung einer solchen Expired - Lifetime DE60135290D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000338068A JP4454830B2 (ja) 2000-11-06 2000-11-06 シーケンス回路

Publications (1)

Publication Number Publication Date
DE60135290D1 true DE60135290D1 (de) 2008-09-25

Family

ID=18813341

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60135290T Expired - Lifetime DE60135290D1 (de) 2000-11-06 2001-10-26 Sequenzschaltung und Halbleiteranordnung unter Verwendung einer solchen

Country Status (6)

Country Link
US (1) US6483756B2 (de)
EP (1) EP1204119B1 (de)
JP (1) JP4454830B2 (de)
KR (1) KR100667716B1 (de)
DE (1) DE60135290D1 (de)
TW (1) TW512414B (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050213268A1 (en) * 2004-03-26 2005-09-29 Joseph Cetin Method and circuit for improving device power up timing and predictability
JP4413689B2 (ja) * 2004-06-11 2010-02-10 富士通マイクロエレクトロニクス株式会社 電源起動シーケンスを有する半導体集積回路装置
JP5157310B2 (ja) * 2007-08-09 2013-03-06 富士通セミコンダクター株式会社 内部電源回路
JP2009260804A (ja) * 2008-04-18 2009-11-05 Toshiba Corp パワーオン検知回路およびレベル変換回路
TWI371685B (en) * 2008-06-30 2012-09-01 Asustek Comp Inc Power supply system and power supplying method of computer
JP5251499B2 (ja) 2008-12-26 2013-07-31 富士通セミコンダクター株式会社 半導体装置、半導体装置の起動制御方法、及びシステム
ES2373851T3 (es) 2009-09-23 2012-02-09 St-Ericsson Sa Mecanismo de arranque de suministro de energía, aparato, y método para controlar la activación de circuitos de suministro de energía.

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5650976A (en) * 1993-05-14 1997-07-22 Micron Technology, Inc. Dual strobed negative pumped wordlines for dynamic random access memories
EP0787993A4 (de) * 1995-08-21 1999-09-15 Matsushita Electronics Corp Spannungsdetektor , strom-ein-/aus-rücksetzschaltung und halbleitergerät
US5864507A (en) * 1996-12-18 1999-01-26 Cypress Semiconductor Corporation Dual level wordline clamp for reduced memory cell current
US6094395A (en) * 1998-03-27 2000-07-25 Infineon Technologies North America Corp. Arrangement for controlling voltage generators in multi-voltage generator chips such as DRAMs
US5933374A (en) * 1998-06-15 1999-08-03 Siemens Aktiengesellschaft Memory with reduced wire connections

Also Published As

Publication number Publication date
EP1204119B1 (de) 2008-08-13
US6483756B2 (en) 2002-11-19
KR20020035464A (ko) 2002-05-11
US20020054517A1 (en) 2002-05-09
JP4454830B2 (ja) 2010-04-21
TW512414B (en) 2002-12-01
KR100667716B1 (ko) 2007-01-15
JP2002152025A (ja) 2002-05-24
EP1204119A2 (de) 2002-05-08
EP1204119A3 (de) 2004-02-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

Owner name: KABUSHIKI KAISHA TOSHIBA, TOKYO, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE