DE60035630D1 - Hierarchische Vorausladung in Halbleiterspeicheranordnungen - Google Patents
Hierarchische Vorausladung in HalbleiterspeicheranordnungenInfo
- Publication number
- DE60035630D1 DE60035630D1 DE60035630T DE60035630T DE60035630D1 DE 60035630 D1 DE60035630 D1 DE 60035630D1 DE 60035630 T DE60035630 T DE 60035630T DE 60035630 T DE60035630 T DE 60035630T DE 60035630 D1 DE60035630 D1 DE 60035630D1
- Authority
- DE
- Germany
- Prior art keywords
- hierarchical
- semiconductor memory
- memory arrangements
- advance charge
- charge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US333539 | 1994-11-01 | ||
US11971399P | 1999-02-11 | 1999-02-11 | |
US119713 | 1999-02-11 | ||
US09/333,539 US6081479A (en) | 1999-06-15 | 1999-06-15 | Hierarchical prefetch for semiconductor memories |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60035630D1 true DE60035630D1 (de) | 2007-09-06 |
DE60035630T2 DE60035630T2 (de) | 2008-02-07 |
Family
ID=26817618
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60035630T Expired - Lifetime DE60035630T2 (de) | 1999-02-11 | 2000-01-22 | Hierarchische Vorausladung in Halbleiterspeicheranordnungen |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1028427B1 (de) |
JP (1) | JP2000251468A (de) |
KR (1) | KR100393465B1 (de) |
CN (1) | CN1279541C (de) |
DE (1) | DE60035630T2 (de) |
TW (1) | TW495763B (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100490657B1 (ko) * | 2000-12-30 | 2005-05-24 | 주식회사 하이닉스반도체 | 메모리 출력능력의 가변제어 장치 및 방법 |
KR100578233B1 (ko) * | 2000-12-30 | 2006-05-12 | 주식회사 하이닉스반도체 | 동기식메모리장치의 데이터 입출력 가변제어장치 |
JP2002304886A (ja) * | 2001-04-06 | 2002-10-18 | Nec Corp | 半導体記憶装置 |
KR100510512B1 (ko) | 2002-11-18 | 2005-08-26 | 삼성전자주식회사 | 이중 데이터율 동기식 반도체 장치의 데이터 출력 회로 및그 방법 |
JP4607444B2 (ja) * | 2002-11-18 | 2011-01-05 | 三星電子株式会社 | 半導体装置、データ検索回路、メモリセルアレイ判読方法、およびデータ検索方法 |
WO2005045846A1 (ja) * | 2003-11-06 | 2005-05-19 | International Business Machines Corporation | 半導体記憶装置及びそのバースト動作方法 |
US7358872B2 (en) | 2005-09-01 | 2008-04-15 | Micron Technology, Inc. | Method and apparatus for converting parallel data to serial data in high speed applications |
US7613883B2 (en) * | 2006-03-10 | 2009-11-03 | Rambus Inc. | Memory device with mode-selectable prefetch and clock-to-core timing |
CN109872743A (zh) * | 2019-03-19 | 2019-06-11 | 济南德欧雅安全技术有限公司 | 一种基础工艺存储器 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60175293A (ja) * | 1984-02-21 | 1985-09-09 | Toshiba Corp | 半導体メモリ |
DE3543911A1 (de) * | 1984-12-14 | 1986-06-26 | Mitsubishi Denki K.K., Tokio/Tokyo | Digitale verzoegerungseinheit |
WO1988009995A1 (en) * | 1987-06-02 | 1988-12-15 | Hughes Aircraft Company | Pipeline memory structure |
JPH08212778A (ja) * | 1995-02-09 | 1996-08-20 | Mitsubishi Electric Corp | 同期型半導体記憶装置およびそのデータ読出方法 |
JPH08221978A (ja) * | 1995-02-13 | 1996-08-30 | Hitachi Ltd | 半導体記憶装置 |
JP3351692B2 (ja) * | 1995-09-12 | 2002-12-03 | 株式会社東芝 | シンクロナス半導体メモリ装置 |
JPH09223389A (ja) * | 1996-02-15 | 1997-08-26 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
US5784705A (en) * | 1996-07-15 | 1998-07-21 | Mosys, Incorporated | Method and structure for performing pipeline burst accesses in a semiconductor memory |
-
2000
- 2000-01-22 DE DE60035630T patent/DE60035630T2/de not_active Expired - Lifetime
- 2000-01-22 EP EP00101322A patent/EP1028427B1/de not_active Expired - Lifetime
- 2000-02-10 JP JP2000034052A patent/JP2000251468A/ja not_active Withdrawn
- 2000-02-11 KR KR10-2000-0006379A patent/KR100393465B1/ko active IP Right Grant
- 2000-02-12 CN CNB001023217A patent/CN1279541C/zh not_active Expired - Lifetime
- 2000-04-26 TW TW089102205A patent/TW495763B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20000062543A (ko) | 2000-10-25 |
CN1279541C (zh) | 2006-10-11 |
EP1028427B1 (de) | 2007-07-25 |
CN1263347A (zh) | 2000-08-16 |
EP1028427A1 (de) | 2000-08-16 |
KR100393465B1 (ko) | 2003-08-06 |
JP2000251468A (ja) | 2000-09-14 |
DE60035630T2 (de) | 2008-02-07 |
TW495763B (en) | 2002-07-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8327 | Change in the person/name/address of the patent owner |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, A, US Owner name: QIMONDA NORTH AMERICA CORP., CARY, N.C., US |
|
8364 | No opposition during term of opposition | ||
R082 | Change of representative |
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