DE60033598T2 - Halbleiterspeichervorrichtung - Google Patents

Halbleiterspeichervorrichtung Download PDF

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Publication number
DE60033598T2
DE60033598T2 DE60033598T DE60033598T DE60033598T2 DE 60033598 T2 DE60033598 T2 DE 60033598T2 DE 60033598 T DE60033598 T DE 60033598T DE 60033598 T DE60033598 T DE 60033598T DE 60033598 T2 DE60033598 T2 DE 60033598T2
Authority
DE
Germany
Prior art keywords
parallel
memory
output
serial conversion
conversion circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60033598T
Other languages
German (de)
English (en)
Other versions
DE60033598D1 (de
Inventor
Ryuji Kawasaki-shi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE60033598D1 publication Critical patent/DE60033598D1/de
Application granted granted Critical
Publication of DE60033598T2 publication Critical patent/DE60033598T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE60033598T 1999-08-02 2000-03-23 Halbleiterspeichervorrichtung Expired - Lifetime DE60033598T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP21918899 1999-08-02
JP11219188A JP2001043700A (ja) 1999-08-02 1999-08-02 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE60033598D1 DE60033598D1 (de) 2007-04-12
DE60033598T2 true DE60033598T2 (de) 2007-06-21

Family

ID=16731596

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60033598T Expired - Lifetime DE60033598T2 (de) 1999-08-02 2000-03-23 Halbleiterspeichervorrichtung

Country Status (4)

Country Link
US (1) US6301182B1 (enExample)
EP (1) EP1074991B1 (enExample)
JP (1) JP2001043700A (enExample)
DE (1) DE60033598T2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100551658B1 (ko) * 2001-04-02 2006-02-13 가부시키가이샤 히타치세이사쿠쇼 반도체 장치 및 그 제조 방법
US7313639B2 (en) * 2003-01-13 2007-12-25 Rambus Inc. Memory system and device with serialized data transfer
KR20040105060A (ko) * 2003-06-04 2004-12-14 삼성전자주식회사 유효 출력 데이터 윈도우（Ｖａｌｉｄ ｏｕｔｐｕｔｄａｔａ ｗｉｎｄｏｗ）를 확장시킬 수 있는 출력회로를구비하는 동기식 메모리장치 및 유효 출력 데이터 윈도우확장 방법
US20060080518A1 (en) * 2004-10-08 2006-04-13 Richard Dellacona Method for securing computers from malicious code attacks
US20070022333A1 (en) * 2005-06-17 2007-01-25 Terry Steven W Testing of interconnects associated with memory cards
US20070000070A1 (en) * 2005-06-30 2007-01-04 Vena Lou Ann C Method and kit for applying lowlights to hair
US20070063741A1 (en) * 2005-09-22 2007-03-22 Tarango Tony M Testing of integrated circuit receivers
US20070094554A1 (en) * 2005-10-20 2007-04-26 Martin Versen Chip specific test mode execution on a memory module
US7802157B2 (en) * 2006-06-22 2010-09-21 Micron Technology, Inc. Test mode for multi-chip integrated circuit packages
US7945827B1 (en) * 2006-12-28 2011-05-17 Marvell International Technology Ltd. Method and device for scan chain management of dies reused in a multi-chip package
KR101184312B1 (ko) 2007-05-14 2012-09-21 가부시키가이샤 어드밴티스트 시험 장치

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0652640B2 (ja) 1984-12-18 1994-07-06 富士通株式会社 メモリを内蔵した半導体集積回路
JPH0282174A (ja) * 1988-09-19 1990-03-22 Hitachi Ltd 半導体集積回路装置
JPH02246151A (ja) * 1989-03-20 1990-10-01 Hitachi Ltd 抵抗手段と論理回路、入力回路、ヒューズ切断回路、駆動回路、電源回路、静電保護回路及びこれらを含む半導体記憶装置ならびにそのレイアウト方式及びテスト方式
JPH05172390A (ja) * 1991-12-19 1993-07-09 Sanyo Electric Co Ltd 空気調和機の制御装置
DE19711097C2 (de) 1997-03-17 2000-04-06 Siemens Ag Integrierte Schaltung mit einem Speicher und einer Prüfschaltung
US5862146A (en) 1997-04-15 1999-01-19 Texas Instruments Incorporated Process of testing memory parts and equipment for conducting the testing
KR100238256B1 (ko) * 1997-12-03 2000-01-15 윤종용 직접 억세스 모드 테스트를 사용하는 메모리 장치 및 테스트방법

Also Published As

Publication number Publication date
EP1074991A2 (en) 2001-02-07
JP2001043700A (ja) 2001-02-16
EP1074991B1 (en) 2007-02-28
EP1074991A3 (en) 2001-03-28
DE60033598D1 (de) 2007-04-12
US6301182B1 (en) 2001-10-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE