DE60033339D1 - Verfahren zur Überwachung des Takts und Vorrichtung zur Datenübertragung, die das Verfahren verwendet - Google Patents

Verfahren zur Überwachung des Takts und Vorrichtung zur Datenübertragung, die das Verfahren verwendet

Info

Publication number
DE60033339D1
DE60033339D1 DE60033339T DE60033339T DE60033339D1 DE 60033339 D1 DE60033339 D1 DE 60033339D1 DE 60033339 T DE60033339 T DE 60033339T DE 60033339 T DE60033339 T DE 60033339T DE 60033339 D1 DE60033339 D1 DE 60033339D1
Authority
DE
Germany
Prior art keywords
clock
monitoring
data transmission
transmission
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60033339T
Other languages
English (en)
Other versions
DE60033339T2 (de
Inventor
Takanori Saeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Application granted granted Critical
Publication of DE60033339D1 publication Critical patent/DE60033339D1/de
Publication of DE60033339T2 publication Critical patent/DE60033339T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/19—Monitoring patterns of pulse trains
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00052—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter by mixing the outputs of fixed delayed signals with each other or with the input signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE60033339T 1999-06-24 2000-06-24 Verfahren zur Überwachung des Takts und Vorrichtung zur Datenübertragung, die das Verfahren verwendet Expired - Lifetime DE60033339T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP17838299A JP3573661B2 (ja) 1999-06-24 1999-06-24 クロック信号制御方法及び回路とこれを用いたデータ伝送装置
JP17838299 1999-06-24

Publications (2)

Publication Number Publication Date
DE60033339D1 true DE60033339D1 (de) 2007-03-29
DE60033339T2 DE60033339T2 (de) 2007-10-31

Family

ID=16047524

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60033339T Expired - Lifetime DE60033339T2 (de) 1999-06-24 2000-06-24 Verfahren zur Überwachung des Takts und Vorrichtung zur Datenübertragung, die das Verfahren verwendet

Country Status (8)

Country Link
US (1) US6340910B1 (de)
EP (1) EP1063810B1 (de)
JP (1) JP3573661B2 (de)
KR (1) KR100411441B1 (de)
CN (1) CN100399735C (de)
CA (1) CA2312106A1 (de)
DE (1) DE60033339T2 (de)
TW (1) TW454387B (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3519693B2 (ja) * 2000-04-04 2004-04-19 松下電器産業株式会社 多相クロック信号発生回路
JP3838890B2 (ja) * 2001-08-21 2006-10-25 Ｎｅｃエレクトロニクス株式会社 半導体集積回路とその設計方法
JP3849485B2 (ja) 2001-10-18 2006-11-22 セイコーエプソン株式会社 パルス処理回路および周波数逓倍回路
JP3960271B2 (ja) * 2003-07-02 2007-08-15 ソニー株式会社 位相誤差判定方法、デジタルｐｌｌ装置
JP2005050123A (ja) * 2003-07-28 2005-02-24 Nec Micro Systems Ltd スキュー補正回路
JP4703997B2 (ja) * 2004-09-28 2011-06-15 富士通セミコンダクター株式会社 半導体集積回路
KR100641360B1 (ko) 2004-11-08 2006-11-01 삼성전자주식회사 지연 동기 루프 및 이를 구비한 반도체 메모리 장치
TWI265703B (en) * 2004-12-22 2006-11-01 Prolific Technology Inc A system and method of clock architecture of oversampling high speed clock/data recovery
KR100809714B1 (ko) * 2007-01-03 2008-03-06 삼성전자주식회사 멀티 위상 생성 방법 및 이에 적합한 장치
KR20090045495A (ko) 2007-11-02 2009-05-08 주식회사 하이닉스반도체 클럭 조절회로 및 이를 포함하는 데이터 정렬회로
KR100904236B1 (ko) 2007-11-06 2009-06-25 주식회사 부방테크론 최소 스위칭 오프 시간을 보장하는 ｉｈ 회로 제어 장치
KR100967103B1 (ko) * 2008-06-30 2010-07-05 주식회사 하이닉스반도체 클럭생성회로 및 클럭생성방법
JP5442723B2 (ja) 2009-05-13 2014-03-12 パナソニック株式会社 ハイブリッド型データ送信回路
GB2488063B (en) * 2009-11-20 2015-08-26 Anue Systems Inc Method, system and computer program product for measuring a communication from a first device to a second device
JP5910383B2 (ja) * 2012-07-19 2016-04-27 株式会社ソシオネクスト スキュー低減回路
CA3061786C (en) 2018-11-20 2024-03-19 Square Grove Llc Vertically adjustable desk with under-carriage mounting system
CN112462848B (zh) * 2020-12-07 2024-04-09 深圳供电局有限公司 时钟偏差校正方法、装置及计算机设备

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594900B2 (ja) * 1979-09-03 1984-02-01 日本電気株式会社 クロック再生回路
US4669024A (en) * 1985-10-23 1987-05-26 Westinghouse Electric Corp. Multiphase frequency selective phase locked loop with multiphase sinusoidal and digital outputs
US4963839A (en) * 1989-09-01 1990-10-16 Westinghouse Electric Corp. Wide bandwidth phase locked loop circuit with sliding window averager
JP3315134B2 (ja) * 1991-09-05 2002-08-19 株式会社日立製作所 多トラック位相同期装置
JP3321926B2 (ja) * 1993-09-17 2002-09-09 株式会社日立製作所 自己同期型半導体集積回路装置
JP2806863B2 (ja) * 1996-02-27 1998-09-30 日本電気エンジニアリング株式会社 ビット同期回路
JP3125699B2 (ja) 1996-12-25 2001-01-22 日本電気株式会社 データ同期回路
KR100240278B1 (ko) * 1997-02-14 2000-01-15 김영환 엘시디 드라이버용 클럭발생회로
JP3678541B2 (ja) * 1997-06-12 2005-08-03 富士通株式会社 位相補正回路、位相補正ｄｌｌ回路、多位相クロック生成ｄｌｌ回路及び半導体装置
JP2978856B2 (ja) * 1997-09-29 1999-11-15 山形日本電気株式会社 水平走査パルス信号制御回路
US5923613A (en) * 1998-03-18 1999-07-13 Etron Technology, Inc. Latched type clock synchronizer with additional 180°-phase shift clock

Also Published As

Publication number Publication date
CN1279550A (zh) 2001-01-10
DE60033339T2 (de) 2007-10-31
CN100399735C (zh) 2008-07-02
EP1063810A2 (de) 2000-12-27
EP1063810B1 (de) 2007-02-14
JP3573661B2 (ja) 2004-10-06
KR100411441B1 (ko) 2003-12-18
EP1063810A3 (de) 2004-11-24
TW454387B (en) 2001-09-11
US6340910B1 (en) 2002-01-22
KR20010021020A (ko) 2001-03-15
CA2312106A1 (en) 2000-12-24
JP2001007686A (ja) 2001-01-12

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