DE4006144C2 - - Google Patents

Info

Publication number
DE4006144C2
DE4006144C2 DE4006144A DE4006144A DE4006144C2 DE 4006144 C2 DE4006144 C2 DE 4006144C2 DE 4006144 A DE4006144 A DE 4006144A DE 4006144 A DE4006144 A DE 4006144A DE 4006144 C2 DE4006144 C2 DE 4006144C2
Authority
DE
Germany
Prior art keywords
level
transistor
signal
pmos transistor
pmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE4006144A
Other languages
German (de)
English (en)
Other versions
DE4006144A1 (de
Inventor
Yong-Bo Busan Kr Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE4006144A1 publication Critical patent/DE4006144A1/de
Application granted granted Critical
Publication of DE4006144C2 publication Critical patent/DE4006144C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
DE4006144A 1989-10-26 1990-02-27 Pegelumsetzer Granted DE4006144A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890015443A KR920006251B1 (ko) 1989-10-26 1989-10-26 레벨변환기

Publications (2)

Publication Number Publication Date
DE4006144A1 DE4006144A1 (de) 1991-05-23
DE4006144C2 true DE4006144C2 (ja) 1992-03-05

Family

ID=19291059

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4006144A Granted DE4006144A1 (de) 1989-10-26 1990-02-27 Pegelumsetzer

Country Status (5)

Country Link
JP (1) JPH03147419A (ja)
KR (1) KR920006251B1 (ja)
DE (1) DE4006144A1 (ja)
FR (1) FR2653951B1 (ja)
GB (1) GB2238681B (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007005403A1 (de) 2007-02-03 2008-08-07 Man Roland Druckmaschinen Ag Trennsaugereinrichtung für eine Bogendruckmaschine
DE202010003265U1 (de) 2010-03-08 2010-05-27 Manroland Ag Saugerkopf
DE202011001879U1 (de) 2010-12-16 2011-03-24 Manroland Ag Saugereinrichtung

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4127212A1 (de) * 1991-08-16 1993-02-18 Licentia Gmbh Schaltungsanordnung zur pegelumsetzung
KR940005509B1 (ko) * 1992-02-14 1994-06-20 삼성전자 주식회사 승압단속회로및이를구비하는출력버퍼회로
JP3038094B2 (ja) * 1992-12-24 2000-05-08 三菱電機株式会社 半導体集積回路装置の出力回路

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4258272A (en) * 1979-03-19 1981-03-24 National Semiconductor Corporation TTL to CMOS input buffer circuit
JPS5873233A (ja) * 1981-10-28 1983-05-02 Nec Corp 半導体集積回路
JPS58184821A (ja) * 1982-03-31 1983-10-28 Fujitsu Ltd 昇圧回路
US4501978A (en) * 1982-11-24 1985-02-26 Rca Corporation Level shift interface circuit
JPS6162230A (ja) * 1984-09-04 1986-03-31 Seiko Epson Corp インタ−フエ−ス回路
US4593212A (en) * 1984-12-28 1986-06-03 Motorola, Inc. TTL to CMOS input buffer
JPS61170125A (ja) * 1985-01-23 1986-07-31 Oki Electric Ind Co Ltd 出力回路
JPS6213120A (ja) * 1985-07-10 1987-01-21 Mitsubishi Electric Corp 半導体装置
JPS6269719A (ja) * 1985-09-24 1987-03-31 Toshiba Corp レベル変換論理回路
US4689505A (en) * 1986-11-13 1987-08-25 Microelectronics And Computer Technology Corporation High speed bootstrapped CMOS driver

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007005403A1 (de) 2007-02-03 2008-08-07 Man Roland Druckmaschinen Ag Trennsaugereinrichtung für eine Bogendruckmaschine
DE202010003265U1 (de) 2010-03-08 2010-05-27 Manroland Ag Saugerkopf
DE202011001879U1 (de) 2010-12-16 2011-03-24 Manroland Ag Saugereinrichtung

Also Published As

Publication number Publication date
GB2238681A (en) 1991-06-05
JPH03147419A (ja) 1991-06-24
GB9004352D0 (en) 1990-04-25
GB2238681B (en) 1994-03-23
FR2653951A1 (fr) 1991-05-03
KR920006251B1 (ko) 1992-08-01
FR2653951B1 (fr) 1992-02-14
KR910008842A (ko) 1991-05-31
DE4006144A1 (de) 1991-05-23

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee