DE68918164T2 - Integrierte Halbleiterschaltung mit einem CMOS-Inverter. - Google Patents

Integrierte Halbleiterschaltung mit einem CMOS-Inverter.

Info

Publication number
DE68918164T2
DE68918164T2 DE68918164T DE68918164T DE68918164T2 DE 68918164 T2 DE68918164 T2 DE 68918164T2 DE 68918164 T DE68918164 T DE 68918164T DE 68918164 T DE68918164 T DE 68918164T DE 68918164 T2 DE68918164 T2 DE 68918164T2
Authority
DE
Germany
Prior art keywords
semiconductor circuit
cmos inverter
integrated semiconductor
integrated
cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68918164T
Other languages
English (en)
Other versions
DE68918164D1 (de
Inventor
Harumi Shizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Publication of DE68918164D1 publication Critical patent/DE68918164D1/de
Application granted granted Critical
Publication of DE68918164T2 publication Critical patent/DE68918164T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
DE68918164T 1988-06-17 1989-06-14 Integrierte Halbleiterschaltung mit einem CMOS-Inverter. Expired - Fee Related DE68918164T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63150848A JP2542678B2 (ja) 1988-06-17 1988-06-17 半導体装置

Publications (2)

Publication Number Publication Date
DE68918164D1 DE68918164D1 (de) 1994-10-20
DE68918164T2 true DE68918164T2 (de) 1995-04-27

Family

ID=15505701

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68918164T Expired - Fee Related DE68918164T2 (de) 1988-06-17 1989-06-14 Integrierte Halbleiterschaltung mit einem CMOS-Inverter.

Country Status (5)

Country Link
US (1) US5073727A (de)
EP (1) EP0346876B1 (de)
JP (1) JP2542678B2 (de)
KR (1) KR930000972B1 (de)
DE (1) DE68918164T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3194982B2 (ja) * 1991-04-17 2001-08-06 ヤマハ発動機株式会社 エンジンのバルブリフタの製造方法
US5319260A (en) * 1991-07-23 1994-06-07 Standard Microsystems Corporation Apparatus and method to prevent the disturbance of a quiescent output buffer caused by ground bounce or by power bounce induced by neighboring active output buffers
KR940010671B1 (ko) * 1992-07-25 1994-10-24 금성일렉트론 주식회사 Cmos 3-스테이트 버퍼회로 및 그 제어방법
JPH06224734A (ja) * 1992-12-01 1994-08-12 Nec Corp 入力回路
GB9404013D0 (en) * 1994-03-02 1994-04-20 Inmos Ltd Current generating unit
DE69503205T2 (de) * 1994-03-25 1999-02-11 Philips Norden Ab Cmos eingang mit vcc-kompensierter dynamischer schwelle
JP3229164B2 (ja) * 1994-07-28 2001-11-12 インターナショナル・ビジネス・マシーンズ・コーポレーション ラッチ回路
US5491429A (en) * 1994-09-16 1996-02-13 At&T Global Information Solutions Company Apparatus for reducing current consumption in a CMOS inverter circuit
US5514979A (en) * 1994-11-28 1996-05-07 Unisys Corporation Methods and apparatus for dynamically reducing ringing of driver output signal
FR2730367A1 (fr) * 1995-02-08 1996-08-09 Bull Sa Coupleur d'entree sortie de circuit integre
JP3618424B2 (ja) * 1995-09-07 2005-02-09 エイ・アイ・エル株式会社 低消費電力論理回路
JP2005518699A (ja) * 2002-02-21 2005-06-23 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 低減された基板バウンスを有する集積回路
US6870895B2 (en) * 2002-12-19 2005-03-22 Semiconductor Energy Laboratory Co., Ltd. Shift register and driving method thereof
KR100549872B1 (ko) * 2003-12-10 2006-02-06 삼성전자주식회사 차동 스위칭 회로 및 디지털 아날로그 변환기
KR20070012972A (ko) * 2005-07-25 2007-01-30 삼성전자주식회사 표시 장치, 그 구동 장치 및 방법
US8415972B2 (en) * 2010-11-17 2013-04-09 Advanced Micro Devices, Inc. Variable-width power gating module
US8384421B1 (en) 2011-04-21 2013-02-26 Applied Micro Circuits Corporation Digital CMOS circuit with noise cancellation
US8773880B2 (en) 2011-06-23 2014-07-08 Netlogic Microsystems, Inc. Content addressable memory array having virtual ground nodes
US8837188B1 (en) 2011-06-23 2014-09-16 Netlogic Microsystems, Inc. Content addressable memory row having virtual ground and charge sharing
US20200136595A1 (en) * 2018-10-29 2020-04-30 Stmicroelectronics International N.V. Schmitt trigger circuit with independent control over high and low trip points using a split architecture

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4490627A (en) * 1982-11-17 1984-12-25 Motorola, Inc. Schmitt trigger circuit
US4687954A (en) * 1984-03-06 1987-08-18 Kabushiki Kaisha Toshiba CMOS hysteresis circuit with enable switch or natural transistor
JPS61292412A (ja) * 1985-06-20 1986-12-23 Fujitsu Ltd 出力回路
JPH0720060B2 (ja) * 1985-08-14 1995-03-06 株式会社東芝 出力回路装置
US4638187A (en) * 1985-10-01 1987-01-20 Vtc Incorporated CMOS output buffer providing high drive current with minimum output signal distortion
US4649295A (en) * 1986-01-13 1987-03-10 Motorola, Inc. BIMOS logic gate
JPS62220026A (ja) * 1986-03-20 1987-09-28 Toshiba Corp 出力バツフア回路
JPS635553A (ja) * 1986-06-25 1988-01-11 Fujitsu Ltd バツフア回路
US4749882A (en) * 1986-07-25 1988-06-07 Digital Equipment Corporation Apparatus and method for applying rapid transient signals to components on a printed circuit board
US4731553A (en) * 1986-09-30 1988-03-15 Texas Instruments Incorporated CMOS output buffer having improved noise characteristics
US4739193A (en) * 1986-10-30 1988-04-19 Rca Corporation Drive circuit with limited signal transition rate for RFI reduction
JPS63236407A (ja) * 1987-03-25 1988-10-03 Toshiba Corp 半導体回路
US4829199A (en) * 1987-07-13 1989-05-09 Ncr Corporation Driver circuit providing load and time adaptive current
US4818901A (en) * 1987-07-20 1989-04-04 Harris Corporation Controlled switching CMOS output buffer
US4820942A (en) * 1988-01-27 1989-04-11 Advanced Micro Devices, Inc. High-speed, high-drive output buffer circuits with reduced ground bounce
US4857770A (en) * 1988-02-29 1989-08-15 Advanced Micro Devices, Inc. Output buffer arrangement for reducing chip noise without speed penalty

Also Published As

Publication number Publication date
DE68918164D1 (de) 1994-10-20
JP2542678B2 (ja) 1996-10-09
JPH024008A (ja) 1990-01-09
KR930000972B1 (ko) 1993-02-11
EP0346876A1 (de) 1989-12-20
KR900001042A (ko) 1990-01-31
EP0346876B1 (de) 1994-09-14
US5073727A (en) 1991-12-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee