DE3885587D1 - Verfahren zum Herstellen einer integrierten Schaltung mit MOS-Transistoren mittlerer Spannung. - Google Patents

Verfahren zum Herstellen einer integrierten Schaltung mit MOS-Transistoren mittlerer Spannung.

Info

Publication number
DE3885587D1
DE3885587D1 DE88420417T DE3885587T DE3885587D1 DE 3885587 D1 DE3885587 D1 DE 3885587D1 DE 88420417 T DE88420417 T DE 88420417T DE 3885587 T DE3885587 T DE 3885587T DE 3885587 D1 DE3885587 D1 DE 3885587D1
Authority
DE
Germany
Prior art keywords
manufacturing
integrated circuit
mos transistors
medium voltage
voltage mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88420417T
Other languages
English (en)
Other versions
DE3885587T2 (de
Inventor
Philippe Boivin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Application granted granted Critical
Publication of DE3885587D1 publication Critical patent/DE3885587D1/de
Publication of DE3885587T2 publication Critical patent/DE3885587T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
DE3885587T 1987-12-14 1988-12-14 Verfahren zum Herstellen einer integrierten Schaltung mit MOS-Transistoren mittlerer Spannung. Expired - Fee Related DE3885587T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8717782A FR2624653B1 (fr) 1987-12-14 1987-12-14 Procede de fabrication d'un circuit integre comprenant des transistors mos moyenne tension

Publications (2)

Publication Number Publication Date
DE3885587D1 true DE3885587D1 (de) 1993-12-16
DE3885587T2 DE3885587T2 (de) 1994-06-16

Family

ID=9358075

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3885587T Expired - Fee Related DE3885587T2 (de) 1987-12-14 1988-12-14 Verfahren zum Herstellen einer integrierten Schaltung mit MOS-Transistoren mittlerer Spannung.

Country Status (6)

Country Link
EP (1) EP0321366B1 (de)
JP (1) JPH022171A (de)
KR (1) KR890011114A (de)
AT (1) ATE97258T1 (de)
DE (1) DE3885587T2 (de)
FR (1) FR2624653B1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3924062C2 (de) * 1989-07-21 1993-11-25 Eurosil Electronic Gmbh EEPROM-Halbleitereinrichtung mit Isolierzonen für Niedervolt-Logikelemente
JP3141446B2 (ja) * 1991-10-08 2001-03-05 日本電気株式会社 半導体装置の製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2123605A (en) * 1982-06-22 1984-02-01 Standard Microsyst Smc MOS integrated circuit structure and method for its fabrication
US4577394A (en) * 1984-10-01 1986-03-25 National Semiconductor Corporation Reduction of field oxide encroachment in MOS fabrication

Also Published As

Publication number Publication date
DE3885587T2 (de) 1994-06-16
FR2624653B1 (fr) 1991-10-11
EP0321366B1 (de) 1993-11-10
ATE97258T1 (de) 1993-11-15
EP0321366A1 (de) 1989-06-21
JPH022171A (ja) 1990-01-08
FR2624653A1 (fr) 1989-06-16
KR890011114A (ko) 1989-08-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee