DE3855252D1 - Verfahren zum Herstellen eines Twin-well-BICMOS-Transistors - Google Patents

Verfahren zum Herstellen eines Twin-well-BICMOS-Transistors

Info

Publication number
DE3855252D1
DE3855252D1 DE3855252T DE3855252T DE3855252D1 DE 3855252 D1 DE3855252 D1 DE 3855252D1 DE 3855252 T DE3855252 T DE 3855252T DE 3855252 T DE3855252 T DE 3855252T DE 3855252 D1 DE3855252 D1 DE 3855252D1
Authority
DE
Germany
Prior art keywords
twin
manufacturing
bicmos transistor
well
well bicmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3855252T
Other languages
English (en)
Other versions
DE3855252T2 (de
Inventor
Robert H Eklund
Robert H Havemann
Roger A Haken
David B Scott
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE3855252D1 publication Critical patent/DE3855252D1/de
Application granted granted Critical
Publication of DE3855252T2 publication Critical patent/DE3855252T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
DE3855252T 1987-12-07 1988-12-06 Verfahren zum Herstellen eines Twin-well-BICMOS-Transistors Expired - Fee Related DE3855252T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12927187A 1987-12-07 1987-12-07

Publications (2)

Publication Number Publication Date
DE3855252D1 true DE3855252D1 (de) 1996-06-05
DE3855252T2 DE3855252T2 (de) 1996-08-14

Family

ID=22439213

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3855252T Expired - Fee Related DE3855252T2 (de) 1987-12-07 1988-12-06 Verfahren zum Herstellen eines Twin-well-BICMOS-Transistors

Country Status (4)

Country Link
EP (1) EP0320217B1 (de)
JP (1) JPH022156A (de)
KR (1) KR0140715B1 (de)
DE (1) DE3855252T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047357A (en) * 1989-02-03 1991-09-10 Texas Instruments Incorporated Method for forming emitters in a BiCMOS process
US5171702A (en) * 1989-07-21 1992-12-15 Texas Instruments Incorporated Method for forming a thick base oxide in a BiCMOS process
EP0409041B1 (de) * 1989-07-21 1995-10-11 Texas Instruments Incorporated Methode zur Bildung eines dicken Basis-Oxids bei BICMOS-Prozessen
US5079177A (en) * 1989-09-19 1992-01-07 National Semiconductor Corporation Process for fabricating high performance bicmos circuits
IT1237666B (it) * 1989-10-31 1993-06-15 Sgs Thomson Microelectronics Processo per la fabbricazione di un componente limitatore della tensione di programmazione e stabilizzatore di tensione incorporato inun dispositivo elettrico con celle di memoria eeprom
EP0545363A1 (de) * 1991-12-06 1993-06-09 National Semiconductor Corporation Herstellungsverfahren für eine integrierte Schaltung und Struktur
EP0849791A1 (de) * 1996-12-20 1998-06-24 Texas Instruments Incorporated Verbesserungen an oder in Bezug auf Halbleiteranordnungen
FR2758004B1 (fr) * 1996-12-27 1999-03-05 Sgs Thomson Microelectronics Transistor bipolaire a isolement dielectrique
JPH11214533A (ja) * 1998-01-29 1999-08-06 Nec Corp 半導体装置の製造方法
US7700405B2 (en) * 2007-02-28 2010-04-20 Freescale Semiconductor, Inc. Microelectronic assembly with improved isolation voltage performance and a method for forming the same
CN112786538B (zh) * 2021-01-15 2023-05-19 深圳市汇芯通信技术有限公司 一种基于GaN HEMT的开关集成芯片与制作方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58159365A (ja) * 1982-03-17 1983-09-21 Nec Corp 半導体集積回路の製造方法
JPS58225663A (ja) * 1982-06-23 1983-12-27 Toshiba Corp 半導体装置の製造方法
US4637125A (en) * 1983-09-22 1987-01-20 Kabushiki Kaisha Toshiba Method for making a semiconductor integrated device including bipolar transistor and CMOS transistor
JPS60123052A (ja) * 1983-12-07 1985-07-01 Hitachi Ltd 半導体装置
DE3474883D1 (en) * 1984-01-16 1988-12-01 Texas Instruments Inc Integrated circuit having bipolar and field effect devices and method of fabrication
JPS60217657A (ja) * 1984-04-12 1985-10-31 Mitsubishi Electric Corp 半導体集積回路装置の製造方法
US4604790A (en) * 1985-04-01 1986-08-12 Advanced Micro Devices, Inc. Method of fabricating integrated circuit structure having CMOS and bipolar devices
US4929992A (en) * 1985-09-18 1990-05-29 Advanced Micro Devices, Inc. MOS transistor construction with self aligned silicided contacts to gate, source, and drain regions

Also Published As

Publication number Publication date
EP0320217B1 (de) 1996-05-01
EP0320217A2 (de) 1989-06-14
DE3855252T2 (de) 1996-08-14
EP0320217A3 (en) 1989-11-23
JPH022156A (ja) 1990-01-08
KR0140715B1 (ko) 1998-07-15
KR890011104A (ko) 1989-08-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee