DE3834361A1 - Anschlussrahmen fuer eine vielzahl von anschluessen - Google Patents

Anschlussrahmen fuer eine vielzahl von anschluessen

Info

Publication number
DE3834361A1
DE3834361A1 DE3834361A DE3834361A DE3834361A1 DE 3834361 A1 DE3834361 A1 DE 3834361A1 DE 3834361 A DE3834361 A DE 3834361A DE 3834361 A DE3834361 A DE 3834361A DE 3834361 A1 DE3834361 A1 DE 3834361A1
Authority
DE
Germany
Prior art keywords
connections
conductors
connection frame
connection
variety
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE3834361A
Other languages
German (de)
English (en)
Other versions
DE3834361C2 (https=
Inventor
Hugo Westerkamp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Logic Products GmbH
Original Assignee
LSI Logic Products GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Products GmbH filed Critical LSI Logic Products GmbH
Priority to DE3834361A priority Critical patent/DE3834361A1/de
Priority to EP89117182A priority patent/EP0363679A3/de
Priority to JP1261933A priority patent/JPH02247089A/ja
Priority to CA002000338A priority patent/CA2000338A1/en
Publication of DE3834361A1 publication Critical patent/DE3834361A1/de
Application granted granted Critical
Publication of DE3834361C2 publication Critical patent/DE3834361C2/de
Priority to US07/952,473 priority patent/US5270570A/en
Priority to US08/375,273 priority patent/US5466967A/en
Priority to US08/554,967 priority patent/US5656854A/en
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Laser Beam Processing (AREA)
  • Lasers (AREA)
  • Wire Bonding (AREA)
DE3834361A 1988-10-10 1988-10-10 Anschlussrahmen fuer eine vielzahl von anschluessen Granted DE3834361A1 (de)

Priority Applications (7)

Application Number Priority Date Filing Date Title
DE3834361A DE3834361A1 (de) 1988-10-10 1988-10-10 Anschlussrahmen fuer eine vielzahl von anschluessen
EP89117182A EP0363679A3 (de) 1988-10-10 1989-09-16 Verfahren zur Herstellung eines Halbleiterbauteils
JP1261933A JPH02247089A (ja) 1988-10-10 1989-10-06 リードフレーム
CA002000338A CA2000338A1 (en) 1988-10-10 1989-10-10 Lead frame for a multiplicity of terminals
US07/952,473 US5270570A (en) 1988-10-10 1992-09-28 Lead frame for a multiplicity of terminals
US08/375,273 US5466967A (en) 1988-10-10 1995-01-19 Lead frame for a multiplicity of terminals
US08/554,967 US5656854A (en) 1988-10-10 1995-11-13 Lead frame for a multiplicity of terminals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3834361A DE3834361A1 (de) 1988-10-10 1988-10-10 Anschlussrahmen fuer eine vielzahl von anschluessen

Publications (2)

Publication Number Publication Date
DE3834361A1 true DE3834361A1 (de) 1990-04-12
DE3834361C2 DE3834361C2 (https=) 1990-08-16

Family

ID=6364724

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3834361A Granted DE3834361A1 (de) 1988-10-10 1988-10-10 Anschlussrahmen fuer eine vielzahl von anschluessen

Country Status (4)

Country Link
EP (1) EP0363679A3 (https=)
JP (1) JPH02247089A (https=)
CA (1) CA2000338A1 (https=)
DE (1) DE3834361A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4101790C1 (en) * 1991-01-18 1992-07-09 Technisch-Wissenschaftliche-Gesellschaft Thiede Und Partner Mbh, O-1530 Teltow, De Chip-support arrangement prodn. - in tape form, in dual-in-line format by film-bond technology
DE102023202636A1 (de) 2023-03-23 2024-09-26 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines strukturierten Leistungsmodul-Schaltungsträgers

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05114685A (ja) * 1991-10-23 1993-05-07 Mitsubishi Electric Corp 半導体装置
EP0623957B1 (en) * 1992-11-24 1999-02-03 Hitachi Construction Machinery Co., Ltd. Lead frame manufacturing method
US5580466A (en) * 1993-04-14 1996-12-03 Hitachi Construction Machinery Co., Ltd. Metal plate processing method, lead frame processing method, lead frame, semiconductor device manufacturing method, and semiconductor device
WO2004085108A1 (ja) * 1993-08-05 2004-10-07 Nobuhiko Tada リードフレーム加工方法及びリードフレーム加工装置
EP0644585A3 (en) * 1993-09-20 1995-10-11 Sumitomo Electric Industries Lead frame and manufacturing process.

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3110235A1 (de) * 1981-03-17 1982-10-21 Trumpf GmbH & Co, 7257 Ditzingen "verfahren und vorrichtung zum brennschneiden mittels eines laserstrahls"
US4476375A (en) * 1982-03-30 1984-10-09 Fujitsu Limited Process for selective cutting of electrical conductive layer by irradiation of energy beam
DE3517438A1 (de) * 1984-06-18 1985-12-19 Dale Electronics, Inc., Columbus, Nebr. Hochleistungswiderstand mit niedrigem widerstandswert
DE3608410A1 (de) * 1986-03-13 1987-09-17 Siemens Ag Herstellung von feinstrukturen fuer die halbleiterkontaktierung
EP0247775A2 (en) * 1986-05-27 1987-12-02 AT&T Corp. Semiconductor package with high density I/O lead connection

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6080260A (ja) * 1983-10-07 1985-05-08 Hitachi Micro Comput Eng Ltd 半導体装置用リ−ドフレ−ムとその製造方法
JPS61216354A (ja) * 1985-03-20 1986-09-26 Shinko Electric Ind Co Ltd リ−ドフレ−ムの製造方法
GB2178894B (en) * 1985-08-06 1988-07-27 Gen Electric Co Plc Preparation of fragile devices
FR2624652B1 (fr) * 1987-12-14 1990-08-31 Sgs Thomson Microelectronics Procede de mise en place sur un support, d'un composant electronique, muni de ses contacts
JPH0777249B2 (ja) * 1988-09-21 1995-08-16 日本電気株式会社 リードフレームの製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3110235A1 (de) * 1981-03-17 1982-10-21 Trumpf GmbH & Co, 7257 Ditzingen "verfahren und vorrichtung zum brennschneiden mittels eines laserstrahls"
US4476375A (en) * 1982-03-30 1984-10-09 Fujitsu Limited Process for selective cutting of electrical conductive layer by irradiation of energy beam
DE3517438A1 (de) * 1984-06-18 1985-12-19 Dale Electronics, Inc., Columbus, Nebr. Hochleistungswiderstand mit niedrigem widerstandswert
DE3608410A1 (de) * 1986-03-13 1987-09-17 Siemens Ag Herstellung von feinstrukturen fuer die halbleiterkontaktierung
EP0247775A2 (en) * 1986-05-27 1987-12-02 AT&T Corp. Semiconductor package with high density I/O lead connection

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4101790C1 (en) * 1991-01-18 1992-07-09 Technisch-Wissenschaftliche-Gesellschaft Thiede Und Partner Mbh, O-1530 Teltow, De Chip-support arrangement prodn. - in tape form, in dual-in-line format by film-bond technology
DE102023202636A1 (de) 2023-03-23 2024-09-26 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines strukturierten Leistungsmodul-Schaltungsträgers

Also Published As

Publication number Publication date
EP0363679A2 (de) 1990-04-18
DE3834361C2 (https=) 1990-08-16
JPH02247089A (ja) 1990-10-02
CA2000338A1 (en) 1990-04-10
EP0363679A3 (de) 1990-07-18

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee