DE3807433A1 - Verfahren zur herstellung von mos-halbleiter-bauteilen - Google Patents

Verfahren zur herstellung von mos-halbleiter-bauteilen

Info

Publication number
DE3807433A1
DE3807433A1 DE3807433A DE3807433A DE3807433A1 DE 3807433 A1 DE3807433 A1 DE 3807433A1 DE 3807433 A DE3807433 A DE 3807433A DE 3807433 A DE3807433 A DE 3807433A DE 3807433 A1 DE3807433 A1 DE 3807433A1
Authority
DE
Germany
Prior art keywords
nitride layer
oxide layer
layer
gate oxide
silicon nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE3807433A
Other languages
German (de)
English (en)
Inventor
Kwang-Heui Yang
Myeon-Koo Kang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Semiconductor and Telecomunications Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Semiconductor and Telecomunications Co Ltd filed Critical Samsung Semiconductor and Telecomunications Co Ltd
Publication of DE3807433A1 publication Critical patent/DE3807433A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
DE3807433A 1987-03-07 1988-03-07 Verfahren zur herstellung von mos-halbleiter-bauteilen Withdrawn DE3807433A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870002063A KR890003218B1 (ko) 1987-03-07 1987-03-07 반도체 장치의 제조방법

Publications (1)

Publication Number Publication Date
DE3807433A1 true DE3807433A1 (de) 1988-09-15

Family

ID=19259923

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3807433A Withdrawn DE3807433A1 (de) 1987-03-07 1988-03-07 Verfahren zur herstellung von mos-halbleiter-bauteilen

Country Status (4)

Country Link
JP (1) JPS63234563A (ko)
KR (1) KR890003218B1 (ko)
DE (1) DE3807433A1 (ko)
GB (1) GB2203592B (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970008354B1 (ko) * 1994-01-12 1997-05-23 엘지반도체 주식회사 선택적 식각방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE756646A (fr) * 1969-11-07 1971-03-01 Semi Conduttori S P A S G S So Procede pour la fabrication de dispositifs discrets a semi-conducteurs ou de circuits integres, et dispositifs obtenus par sa mise en oeuvre
GB1374112A (en) * 1970-09-23 1974-11-13 Texas Instruments Inc Method of fabrication of an insulated gate field effect transistor
US3761327A (en) * 1971-03-19 1973-09-25 Itt Planar silicon gate mos process
JPS60137024A (ja) * 1983-12-26 1985-07-20 Matsushita Electronics Corp 窒化珪素膜のエツチング方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP-Z.: Japan J. Appl Phys., Vol. 17, 1978, No. 4, S. 737, 738 *

Also Published As

Publication number Publication date
GB8804243D0 (en) 1988-03-23
GB2203592A (en) 1988-10-19
KR890003218B1 (ko) 1989-08-26
KR880011916A (ko) 1988-10-31
JPS63234563A (ja) 1988-09-29
GB2203592B (en) 1990-07-04

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: SAMSUNG ELECTRONICS CO., LTD., SUWON, KYONGGI, KR

8130 Withdrawal