DE3772109D1 - Vertikal strukturierter dynamischer speicher hoher dichte. - Google Patents

Vertikal strukturierter dynamischer speicher hoher dichte.

Info

Publication number
DE3772109D1
DE3772109D1 DE8787104940T DE3772109T DE3772109D1 DE 3772109 D1 DE3772109 D1 DE 3772109D1 DE 8787104940 T DE8787104940 T DE 8787104940T DE 3772109 T DE3772109 T DE 3772109T DE 3772109 D1 DE3772109 D1 DE 3772109D1
Authority
DE
Germany
Prior art keywords
high density
density storage
dynamic high
vertically structured
structured dynamic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787104940T
Other languages
English (en)
Inventor
Brian F Fitzgerald
Kimm Yen T Nguyen
Essex Junction Van Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3772109D1 publication Critical patent/DE3772109D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE8787104940T 1986-05-02 1987-04-03 Vertikal strukturierter dynamischer speicher hoher dichte. Expired - Fee Related DE3772109D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/858,787 US4811067A (en) 1986-05-02 1986-05-02 High density vertically structured memory

Publications (1)

Publication Number Publication Date
DE3772109D1 true DE3772109D1 (de) 1991-09-19

Family

ID=25329182

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787104940T Expired - Fee Related DE3772109D1 (de) 1986-05-02 1987-04-03 Vertikal strukturierter dynamischer speicher hoher dichte.

Country Status (8)

Country Link
US (1) US4811067A (de)
EP (1) EP0248993B1 (de)
JP (1) JPH06105769B2 (de)
AU (1) AU586096B2 (de)
BR (1) BR8701781A (de)
CA (1) CA1277031C (de)
DE (1) DE3772109D1 (de)
ES (1) ES2025082B3 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE33972E (en) * 1986-07-15 1992-06-23 International Business Machines Corporation Two square memory cells
JPS63237460A (ja) * 1987-03-25 1988-10-03 Mitsubishi Electric Corp 半導体装置
US5159570A (en) * 1987-12-22 1992-10-27 Texas Instruments Incorporated Four memory state EEPROM
US5001525A (en) * 1989-03-27 1991-03-19 International Business Machines Corporation Two square memory cells having highly conductive word lines
US5192704A (en) * 1989-06-30 1993-03-09 Texas Instruments Incorporated Method and apparatus for a filament channel pass gate ferroelectric capacitor memory cell
US5136534A (en) * 1989-06-30 1992-08-04 Texas Instruments Incorporated Method and apparatus for a filament channel pass gate ferroelectric capacitor memory cell
JPH0821689B2 (ja) * 1990-02-26 1996-03-04 株式会社東芝 半導体記憶装置およびその製造方法
US5760452A (en) * 1991-08-22 1998-06-02 Nec Corporation Semiconductor memory and method of fabricating the same
US5512517A (en) * 1995-04-25 1996-04-30 International Business Machines Corporation Self-aligned gate sidewall spacer in a corrugated FET and method of making same
US5789317A (en) 1996-04-12 1998-08-04 Micron Technology, Inc. Low temperature reflow method for filling high aspect ratio contacts
US7067406B2 (en) * 1997-03-31 2006-06-27 Intel Corporation Thermal conducting trench in a semiconductor structure and method for forming the same
US6222254B1 (en) * 1997-03-31 2001-04-24 Intel Corporation Thermal conducting trench in a semiconductor structure and method for forming the same
US6090661A (en) * 1998-03-19 2000-07-18 Lsi Logic Corporation Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls
US6894343B2 (en) * 2001-05-18 2005-05-17 Sandisk Corporation Floating gate memory cells utilizing substrate trenches to scale down their size
US6936887B2 (en) * 2001-05-18 2005-08-30 Sandisk Corporation Non-volatile memory cells utilizing substrate trenches
KR100526891B1 (ko) * 2004-02-25 2005-11-09 삼성전자주식회사 반도체 소자에서의 버티컬 트랜지스터 구조 및 그에 따른형성방법
DE102004031385B4 (de) * 2004-06-29 2010-12-09 Qimonda Ag Verfahren zur Herstellung von Stegfeldeffekttransistoren in einer DRAM-Speicherzellenanordnung, Feldeffekttransistoren mit gekrümmtem Kanal und DRAM-Speicherzellenanordnung
US7859050B2 (en) * 2007-01-22 2010-12-28 Micron Technology, Inc. Memory having a vertical access device
US11818877B2 (en) 2020-11-02 2023-11-14 Applied Materials, Inc. Three-dimensional dynamic random access memory (DRAM) and methods of forming the same

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
US3841926A (en) * 1973-01-02 1974-10-15 Ibm Integrated circuit fabrication process
US3811076A (en) * 1973-01-02 1974-05-14 Ibm Field effect transistor integrated circuit and memory
US4225945A (en) * 1976-01-12 1980-09-30 Texas Instruments Incorporated Random access MOS memory cell using double level polysilicon
US4222062A (en) * 1976-05-04 1980-09-09 American Microsystems, Inc. VMOS Floating gate memory device
JPS6037619B2 (ja) * 1976-11-17 1985-08-27 株式会社東芝 半導体メモリ装置
DE2706155A1 (de) * 1977-02-14 1978-08-17 Siemens Ag In integrierter technik hergestellter elektronischer speicher
US4276557A (en) * 1978-12-29 1981-06-30 Bell Telephone Laboratories, Incorporated Integrated semiconductor circuit structure and method for making it
US4462040A (en) * 1979-05-07 1984-07-24 International Business Machines Corporation Single electrode U-MOSFET random access memory
US4271418A (en) * 1979-10-29 1981-06-02 American Microsystems, Inc. VMOS Memory cell and method for making same
JPS5681968A (en) * 1979-12-07 1981-07-04 Toshiba Corp Manufacture of semiconductor device
US4295924A (en) * 1979-12-17 1981-10-20 International Business Machines Corporation Method for providing self-aligned conductor in a V-groove device
US4335450A (en) * 1980-01-30 1982-06-15 International Business Machines Corporation Non-destructive read out field effect transistor memory cell system
US4353086A (en) * 1980-05-07 1982-10-05 Bell Telephone Laboratories, Incorporated Silicon integrated circuits
US4364074A (en) * 1980-06-12 1982-12-14 International Business Machines Corporation V-MOS Device with self-aligned multiple electrodes
JPS58213464A (ja) * 1982-06-04 1983-12-12 Nec Corp 半導体装置
JPS5982761A (ja) * 1982-11-04 1984-05-12 Hitachi Ltd 半導体メモリ
KR920010461B1 (ko) * 1983-09-28 1992-11-28 가부시끼가이샤 히다찌세이사꾸쇼 반도체 메모리와 그 제조 방법
EP0169938B1 (de) * 1983-12-15 1989-03-29 Kabushiki Kaisha Toshiba Halbleiterspeichervorrichtung mit einem in einer Rille angeordneten Kondensator
JPS60143496A (ja) * 1983-12-29 1985-07-29 Fujitsu Ltd 半導体記憶装置
EP0164829B1 (de) * 1984-04-19 1988-09-28 Nippon Telegraph And Telephone Corporation Halbleiterspeicherbauelement und Verfahren zur Herstellung
US4663832A (en) * 1984-06-29 1987-05-12 International Business Machines Corporation Method for improving the planarity and passivation in a semiconductor isolation trench arrangement
JPS6155957A (ja) * 1984-08-27 1986-03-20 Toshiba Corp 半導体記憶装置
US4689113A (en) * 1986-03-21 1987-08-25 International Business Machines Corporation Process for forming planar chip-level wiring
US4769786A (en) * 1986-07-15 1988-09-06 International Business Machines Corporation Two square memory cells

Also Published As

Publication number Publication date
BR8701781A (pt) 1988-02-09
EP0248993A1 (de) 1987-12-16
AU7244487A (en) 1987-11-05
US4811067A (en) 1989-03-07
JPH06105769B2 (ja) 1994-12-21
ES2025082B3 (es) 1992-03-16
CA1277031C (en) 1990-11-27
EP0248993B1 (de) 1991-08-14
JPS62262456A (ja) 1987-11-14
AU586096B2 (en) 1989-06-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee