DE3687486D1 - Dynamische speicheranordnung. - Google Patents

Dynamische speicheranordnung.

Info

Publication number
DE3687486D1
DE3687486D1 DE8686109436T DE3687486T DE3687486D1 DE 3687486 D1 DE3687486 D1 DE 3687486D1 DE 8686109436 T DE8686109436 T DE 8686109436T DE 3687486 T DE3687486 T DE 3687486T DE 3687486 D1 DE3687486 D1 DE 3687486D1
Authority
DE
Germany
Prior art keywords
storage arrangement
dynamic storage
dynamic
arrangement
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686109436T
Other languages
English (en)
Other versions
DE3687486T2 (de
Inventor
Yoshihiro Takemae
Masao Nakano
Kimiaki Sato
Nobumi Kodama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE3687486D1 publication Critical patent/DE3687486D1/de
Application granted granted Critical
Publication of DE3687486T2 publication Critical patent/DE3687486T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE8686109436T 1985-07-10 1986-07-10 Dynamische speicheranordnung. Expired - Fee Related DE3687486T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60150094A JPS6212991A (ja) 1985-07-10 1985-07-10 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE3687486D1 true DE3687486D1 (de) 1993-02-25
DE3687486T2 DE3687486T2 (de) 1993-04-29

Family

ID=15489378

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686109436T Expired - Fee Related DE3687486T2 (de) 1985-07-10 1986-07-10 Dynamische speicheranordnung.

Country Status (5)

Country Link
US (1) US4787067A (de)
EP (1) EP0208316B1 (de)
JP (1) JPS6212991A (de)
KR (1) KR910000965B1 (de)
DE (1) DE3687486T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63281296A (ja) * 1987-05-13 1988-11-17 Mitsubishi Electric Corp ダイナミツクｒａｍ
JPH061634B2 (ja) * 1987-07-07 1994-01-05 松下電子工業株式会社 ダイナミック型記憶装置
JPS6484496A (en) * 1987-09-26 1989-03-29 Mitsubishi Electric Corp Semiconductor memory
EP0310712B1 (de) * 1987-10-05 1993-09-01 Océ-Nederland B.V. Integrales Eingang-Ausgangssystem für Rastabtast-Druckeinheit
US5173878A (en) * 1987-11-25 1992-12-22 Kabushiki Kaisha Toshiba Semiconductor memory including address multiplexing circuitry for changing the order of supplying row and column addresses between read and write cycles
JPH01205788A (ja) * 1988-02-12 1989-08-18 Toshiba Corp 半導体集積回路
JPH0221490A (ja) * 1988-07-07 1990-01-24 Oki Electric Ind Co Ltd ダイナミック・ランダム・アクセス・メモリ
JP2646032B2 (ja) * 1989-10-14 1997-08-25 三菱電機株式会社 Ｌｉｆｏ方式の半導体記憶装置およびその制御方法
JPH05234371A (ja) * 1992-02-21 1993-09-10 Fujitsu Ltd ダイナミックｒａｍ
JP2982928B2 (ja) * 1992-04-01 1999-11-29 三菱電機株式会社 半導体記憶装置
US5671392A (en) * 1995-04-11 1997-09-23 United Memories, Inc. Memory device circuit and method for concurrently addressing columns of multiple banks of multi-bank memory array
KR100587690B1 (ko) * 2004-10-13 2006-06-08 삼성전자주식회사 어드레스 버퍼 회로 및 어드레스 버퍼 제어방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3729722A (en) * 1971-09-17 1973-04-24 Gte Automatic Electric Lab Inc Dynamic mode integrated circuit memory with self-initiating refresh means
US4079462A (en) * 1976-05-07 1978-03-14 Intel Corporation Refreshing apparatus for MOS dynamic RAMs
JPS55150192A (en) * 1979-05-08 1980-11-21 Nec Corp Memory unit
JPS58155596A (ja) * 1982-03-10 1983-09-16 Hitachi Ltd ダイナミツク型ｍｏｓｒａｍ
JPS5954096A (ja) * 1982-09-22 1984-03-28 Hitachi Ltd ダイナミツク型ｍｏｓｒａｍ
JPH0787037B2 (ja) * 1984-03-02 1995-09-20 沖電気工業株式会社 半導体メモリ回路のデータ書込方法
US4653030B1 (en) * 1984-08-31 1997-08-26 Texas Instruments Inc Self refresh circuitry for dynamic memory
JPS629591A (ja) * 1985-07-08 1987-01-17 Nec Corp Ｍｏｓダイナミツクｒａｍ

Also Published As

Publication number Publication date
KR910000965B1 (en) 1991-02-19
EP0208316A3 (en) 1990-08-16
JPS6212991A (ja) 1987-01-21
DE3687486T2 (de) 1993-04-29
US4787067A (en) 1988-11-22
EP0208316A2 (de) 1987-01-14
JPH0467719B2 (de) 1992-10-29
EP0208316B1 (de) 1993-01-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee