DE3687984D1 - Programmierbares logik-array und gatter. - Google Patents

Programmierbares logik-array und gatter.

Info

Publication number
DE3687984D1
DE3687984D1 DE8686308496T DE3687984T DE3687984D1 DE 3687984 D1 DE3687984 D1 DE 3687984D1 DE 8686308496 T DE8686308496 T DE 8686308496T DE 3687984 T DE3687984 T DE 3687984T DE 3687984 D1 DE3687984 D1 DE 3687984D1
Authority
DE
Germany
Prior art keywords
gate
programmable logic
logic array
array
programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686308496T
Other languages
English (en)
Other versions
DE3687984T2 (de
Inventor
William E Moss
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE3687984D1 publication Critical patent/DE3687984D1/de
Application granted granted Critical
Publication of DE3687984T2 publication Critical patent/DE3687984T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/003—Changing the DC level
    • H03K5/007—Base line stabilisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
DE8686308496T 1986-07-29 1986-10-31 Programmierbares logik-array und gatter. Expired - Fee Related DE3687984T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/891,514 US4779010A (en) 1986-07-29 1986-07-29 Monostable logic gate in a programmable logic array

Publications (2)

Publication Number Publication Date
DE3687984D1 true DE3687984D1 (de) 1993-04-15
DE3687984T2 DE3687984T2 (de) 1993-07-22

Family

ID=25398331

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686308496T Expired - Fee Related DE3687984T2 (de) 1986-07-29 1986-10-31 Programmierbares logik-array und gatter.

Country Status (4)

Country Link
US (1) US4779010A (de)
EP (1) EP0254786B1 (de)
JP (1) JPS6338325A (de)
DE (1) DE3687984T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4899308A (en) * 1986-12-11 1990-02-06 Fairchild Semiconductor Corporation High density ROM in a CMOS gate array
EP0387461A1 (de) * 1989-03-14 1990-09-19 International Business Machines Corporation BICMOS-Schaltung mit vollem Spannungshub für logische Signale
WO1993013629A1 (en) * 1991-12-26 1993-07-08 Altera Corporation Eprom-based crossbar switch with zero standby power
US5453707A (en) * 1993-01-13 1995-09-26 Nec Corporation Polyphase clock generation circuit
US5508640A (en) * 1993-09-14 1996-04-16 Intergraph Corporation Dynamic CMOS logic circuit with precharge
WO2023074194A1 (ja) 2021-10-29 2023-05-04 富士フイルム株式会社 通風型消音器

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3862440A (en) * 1972-09-14 1975-01-21 Tokyo Shibaura Electric Co Pulse transforming circuit arrangements using a clock pulse responsive delayed inverter means
JPS5449039A (en) * 1977-09-27 1979-04-18 Mitsubishi Electric Corp Logic circuit
JPS5838032A (ja) * 1981-08-13 1983-03-05 Fujitsu Ltd Ｃ―ｍｏｓインバータ駆動用バッファ回路
US4437024A (en) * 1981-10-22 1984-03-13 Rca Corporation Actively controlled input buffer
JPS58121195A (ja) * 1982-01-13 1983-07-19 Nec Corp プリチヤ−ジ信号発生回路
JPS60136420A (ja) * 1983-12-24 1985-07-19 Toshiba Corp Ｃ　ｍｏｓ論理回路

Also Published As

Publication number Publication date
JPS6338325A (ja) 1988-02-18
US4779010A (en) 1988-10-18
EP0254786A1 (de) 1988-02-03
EP0254786B1 (de) 1993-03-10
DE3687984T2 (de) 1993-07-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee