DE3782106T2 - Programmierbares cmos-logik-array. - Google Patents

Programmierbares cmos-logik-array.

Info

Publication number
DE3782106T2
DE3782106T2 DE8787306247T DE3782106T DE3782106T2 DE 3782106 T2 DE3782106 T2 DE 3782106T2 DE 8787306247 T DE8787306247 T DE 8787306247T DE 3782106 T DE3782106 T DE 3782106T DE 3782106 T2 DE3782106 T2 DE 3782106T2
Authority
DE
Germany
Prior art keywords
logic array
cmos logic
programmable cmos
programmable
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787306247T
Other languages
English (en)
Other versions
DE3782106D1 (de
Inventor
Thomas Hon Moy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of DE3782106D1 publication Critical patent/DE3782106D1/de
Application granted granted Critical
Publication of DE3782106T2 publication Critical patent/DE3782106T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
DE8787306247T 1986-07-23 1987-07-15 Programmierbares cmos-logik-array. Expired - Fee Related DE3782106T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/888,796 US4697105A (en) 1986-07-23 1986-07-23 CMOS programmable logic array

Publications (2)

Publication Number Publication Date
DE3782106D1 DE3782106D1 (de) 1992-11-12
DE3782106T2 true DE3782106T2 (de) 1993-03-04

Family

ID=25393915

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787306247T Expired - Fee Related DE3782106T2 (de) 1986-07-23 1987-07-15 Programmierbares cmos-logik-array.

Country Status (7)

Country Link
US (1) US4697105A (de)
EP (1) EP0254474B1 (de)
JP (1) JPH0773209B2 (de)
CA (1) CA1258498A (de)
DE (1) DE3782106T2 (de)
ES (1) ES2035069T3 (de)
HK (1) HK96393A (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1195119B (it) * 1986-08-04 1988-10-12 Cselt Centro Studi Lab Telecom Perfezionamenti alle schiere logi che programmabili dinamiche a struttura nor nor realizzate in tecnolo gia c mos
US4831573A (en) * 1987-03-06 1989-05-16 Altera Corporation Programmable integrated circuit micro-sequencer device
US4760290A (en) * 1987-05-21 1988-07-26 Vlsi Technology, Inc. Synchronous logic array circuit with dummy signal lines for controlling "AND" array output
JPH0193927A (ja) * 1987-10-06 1989-04-12 Fujitsu Ltd プログラム可能な論理回路
US4831285A (en) * 1988-01-19 1989-05-16 National Semiconductor Corporation Self precharging static programmable logic array
JPH01221916A (ja) * 1988-02-29 1989-09-05 Nec Corp プログラマブル・ロジック・アレイ
US4912342A (en) * 1988-05-05 1990-03-27 Altera Corporation Programmable logic device with array blocks with programmable clocking
US5629907A (en) * 1991-06-18 1997-05-13 Dallas Semiconductor Corporation Low power timekeeping system
US5544078A (en) * 1988-06-17 1996-08-06 Dallas Semiconductor Corporation Timekeeping comparison circuitry and dual storage memory cells to detect alarms
US4959646A (en) * 1988-06-17 1990-09-25 Dallas Semiconductor Corporation Dynamic PLA timing circuit
EP0348539A1 (de) * 1988-06-28 1990-01-03 Deutsche ITT Industries GmbH Programmierbares CMOS-Logik-Feld
US4894558A (en) * 1988-10-11 1990-01-16 Nec Electronics Inc. Power saving input buffer for use with a gate array
US4906870A (en) * 1988-10-31 1990-03-06 Atmel Corporation Low power logic array device
CA1298359C (en) * 1989-08-28 1992-03-31 Marc P. Roy High-speed dynamic cmos circuit
US5008569A (en) * 1989-09-11 1991-04-16 Northern Telecom Limited High-speed dynamic CMOS circuit and precharge generator
US5010258A (en) * 1989-09-12 1991-04-23 Kabushiki Kaisha Toshiba Programable logic array using one control clock signal
JP2575899B2 (ja) * 1989-10-26 1997-01-29 株式会社東芝 プリチャージ式論理回路
JPH03231515A (ja) * 1990-02-06 1991-10-15 Mitsubishi Electric Corp プログラマブル論理装置
US5287018A (en) * 1990-09-25 1994-02-15 Dallas Semiconductor Corporation Dynamic PLA time circuit
US5572715A (en) * 1991-02-15 1996-11-05 Cypress Semiconductor Corporation Architecture and circuits for eliminating skews in PLDs
US5121005A (en) * 1991-04-01 1992-06-09 Motorola, Inc. Programmable logic array with delayed active pull-ups on the column conductors
US5221867A (en) * 1991-10-11 1993-06-22 Intel Corporation Programmable logic array with internally generated precharge and evaluation timing
GB9125884D0 (en) * 1991-12-05 1992-02-05 Jones Simon R Digital circuits
US5300831A (en) * 1992-09-04 1994-04-05 Pham Dac C Logic macro and protocol for reduced power consumption during idle state
US5402012A (en) * 1993-04-19 1995-03-28 Vlsi Technology, Inc. Sequentially clocked domino-logic cells
US5579206A (en) * 1993-07-16 1996-11-26 Dallas Semiconductor Corporation Enhanced low profile sockets and module systems
US5528463A (en) * 1993-07-16 1996-06-18 Dallas Semiconductor Corp. Low profile sockets and modules for surface mountable applications
DE60015916D1 (de) 2000-02-14 2004-12-23 St Microelectronics Srl Programmierbare logische Felder
US6416164B1 (en) 2001-07-20 2002-07-09 Picoliter Inc. Acoustic ejection of fluids using large F-number focusing elements
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices
DE112010005538T5 (de) 2009-09-10 2013-03-14 Kitagawa Seiki K.K. Laminatpressvorrichtung, Aushärtungsvorrichtung, Trägerplatte, Laminiersystem und Laminierverfahren

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4233667A (en) * 1978-10-23 1980-11-11 International Business Machines Corporation Demand powered programmable logic array
JPS5897922A (ja) * 1981-12-07 1983-06-10 Toshiba Corp 論理積和回路
US4488229A (en) * 1982-12-08 1984-12-11 At&T Bell Laboratories PLA-Based finite state machine with two-level control timing and same-cycle decision-making capability
US4577190A (en) * 1983-04-11 1986-03-18 At&T Bell Laboratories Programmed logic array with auxiliary pull-up means to increase precharging speed
US4611133A (en) * 1983-05-12 1986-09-09 Codex Corporation High speed fully precharged programmable logic array
US4583012A (en) * 1983-10-20 1986-04-15 General Instrument Corporation Logical circuit array
JPS60233933A (ja) * 1984-05-04 1985-11-20 Nec Corp プログラム可能な論理アレイ
EP0178437A1 (de) * 1984-09-19 1986-04-23 Siemens Aktiengesellschaft Programmierbare Schaltung in dynamischer C-MOS-Technik

Also Published As

Publication number Publication date
US4697105A (en) 1987-09-29
JPS6333923A (ja) 1988-02-13
ES2035069T3 (es) 1993-04-16
DE3782106D1 (de) 1992-11-12
EP0254474B1 (de) 1992-10-07
HK96393A (en) 1993-09-24
CA1258498A (en) 1989-08-15
EP0254474A1 (de) 1988-01-27
JPH0773209B2 (ja) 1995-08-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN

8339 Ceased/non-payment of the annual fee