DE3785833D1 - Logikschaltung. - Google Patents

Logikschaltung.

Info

Publication number
DE3785833D1
DE3785833D1 DE8787117592T DE3785833T DE3785833D1 DE 3785833 D1 DE3785833 D1 DE 3785833D1 DE 8787117592 T DE8787117592 T DE 8787117592T DE 3785833 T DE3785833 T DE 3785833T DE 3785833 D1 DE3785833 D1 DE 3785833D1
Authority
DE
Germany
Prior art keywords
logic circuit
logic
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787117592T
Other languages
English (en)
Other versions
DE3785833T2 (de
Inventor
Masaji Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62159884A external-priority patent/JP2511044B2/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3785833D1 publication Critical patent/DE3785833D1/de
Publication of DE3785833T2 publication Critical patent/DE3785833T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/001—Arrangements for reducing power consumption in bipolar transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
DE87117592T 1986-11-29 1987-11-27 Logikschaltung. Expired - Fee Related DE3785833T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP28507786 1986-11-29
JP62159884A JP2511044B2 (ja) 1986-11-29 1987-06-29 論理回路

Publications (2)

Publication Number Publication Date
DE3785833D1 true DE3785833D1 (de) 1993-06-17
DE3785833T2 DE3785833T2 (de) 1993-10-28

Family

ID=26486545

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87117592T Expired - Fee Related DE3785833T2 (de) 1986-11-29 1987-11-27 Logikschaltung.

Country Status (3)

Country Link
US (1) US4839537A (de)
EP (1) EP0270029B1 (de)
DE (1) DE3785833T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4746817A (en) * 1987-03-16 1988-05-24 International Business Machines Corporation BIFET logic circuit
JPH01129451A (ja) * 1987-11-16 1989-05-22 Fujitsu Ltd 半導体装置
JP2696991B2 (ja) * 1988-09-26 1998-01-14 日本電気株式会社 ＢｉＣＭＯＳ論理回路
US5097153A (en) * 1989-05-11 1992-03-17 Texas Instruments Incorporated TTL compatible BICMOS input circuit
US5134323A (en) * 1990-08-03 1992-07-28 Congdon James E Three terminal noninverting transistor switch
US5070261A (en) * 1990-12-04 1991-12-03 Texas Instruments Incorporated Apparatus and method for translating voltages
US5162672A (en) * 1990-12-24 1992-11-10 Motorola, Inc. Data processor having an output terminal with selectable output impedances
US5218243A (en) * 1991-11-20 1993-06-08 National Semiconductor Corporation Bicmos ttl output buffer circuit with reduced power dissipation
US5604417A (en) * 1991-12-19 1997-02-18 Hitachi, Ltd. Semiconductor integrated circuit device
US5258665A (en) * 1992-05-12 1993-11-02 National Semiconductor Corporation AC Miller-Killer circuit for L→Z transitions
JPH0669782A (ja) * 1992-05-29 1994-03-11 Nec Corp ＢｉＭＩＳ論理回路
US5467455A (en) * 1993-11-03 1995-11-14 Motorola, Inc. Data processing system and method for performing dynamic bus termination
US5426384A (en) * 1993-12-27 1995-06-20 Motorola, Inc. Voltage controlled oscillator (VCO) with symmetrical output and logic gate for use in same
US5528166A (en) * 1995-03-14 1996-06-18 Intel Corporation Pulse controlled impedance compensated output buffer
US5787291A (en) * 1996-02-05 1998-07-28 Motorola, Inc. Low power data processing system for interfacing with an external device and method therefor

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4449063A (en) * 1979-08-29 1984-05-15 Fujitsu Limited Logic circuit with improved switching
JPS5915330A (ja) * 1982-07-16 1984-01-26 Nec Corp 集積論理回路
JPS59202730A (ja) * 1983-05-04 1984-11-16 Hitachi Ltd スイツチング回路
JPS6042935A (ja) * 1983-08-19 1985-03-07 Nec Corp 出力回路
JPS60172821A (ja) * 1984-02-13 1985-09-06 Fujitsu Ltd Ｔｔｌ回路
JPS60217726A (ja) * 1984-04-13 1985-10-31 Hitachi Micro Comput Eng Ltd 論理回路
JPS6235716A (ja) * 1985-08-09 1987-02-16 Hitachi Ltd 半導体集積回路装置
US4638186A (en) * 1985-12-02 1987-01-20 Motorola, Inc. BIMOS logic gate
JPS62230221A (ja) * 1986-03-31 1987-10-08 Toshiba Corp バツフア回路
JPS62254460A (ja) * 1986-04-26 1987-11-06 Toshiba Corp Ｂｉ−ＣＭＯＳ論理回路
JP2747396B2 (ja) * 1992-07-27 1998-05-06 太陽誘電株式会社 電子部品の外観検査装置

Also Published As

Publication number Publication date
EP0270029B1 (de) 1993-05-12
EP0270029A3 (en) 1988-09-07
DE3785833T2 (de) 1993-10-28
US4839537A (en) 1989-06-13
EP0270029A2 (de) 1988-06-08

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Legal Events

Date Code Title Description
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee