DE3687401T2 - Integrierter viterbi-dekoder und verfahren zur pruefung desselben. - Google Patents

Integrierter viterbi-dekoder und verfahren zur pruefung desselben.

Info

Publication number
DE3687401T2
DE3687401T2 DE8686115031T DE3687401T DE3687401T2 DE 3687401 T2 DE3687401 T2 DE 3687401T2 DE 8686115031 T DE8686115031 T DE 8686115031T DE 3687401 T DE3687401 T DE 3687401T DE 3687401 T2 DE3687401 T2 DE 3687401T2
Authority
DE
Germany
Prior art keywords
path
acs
output
signals
viterbi decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686115031T
Other languages
German (de)
English (en)
Other versions
DE3687401D1 (de
Inventor
Tadayoshi Katoh
Kaneyasu Shimoda
Atsushi Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE3687401D1 publication Critical patent/DE3687401D1/de
Application granted granted Critical
Publication of DE3687401T2 publication Critical patent/DE3687401T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/01—Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
DE8686115031T 1985-10-29 1986-10-29 Integrierter viterbi-dekoder und verfahren zur pruefung desselben. Expired - Fee Related DE3687401T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60240667A JPS62101128A (ja) 1985-10-29 1985-10-29 ビタビ復号器の試験方法

Publications (2)

Publication Number Publication Date
DE3687401D1 DE3687401D1 (de) 1993-02-11
DE3687401T2 true DE3687401T2 (de) 1993-05-13

Family

ID=17062909

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686115031T Expired - Fee Related DE3687401T2 (de) 1985-10-29 1986-10-29 Integrierter viterbi-dekoder und verfahren zur pruefung desselben.

Country Status (5)

Country Link
US (1) US4763328A (cg-RX-API-DMAC7.html)
EP (1) EP0221507B1 (cg-RX-API-DMAC7.html)
JP (1) JPS62101128A (cg-RX-API-DMAC7.html)
CA (1) CA1272290A (cg-RX-API-DMAC7.html)
DE (1) DE3687401T2 (cg-RX-API-DMAC7.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10217043A1 (de) * 2002-04-17 2003-11-06 Infineon Technologies Ag Verfahren und Einrichtung zum Testen eines Pfadgedächtnisspeichers des Registeraustausch-Typs sowie testfähiger Pfadgedächtnisspeicher

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043990A (en) * 1987-12-04 1991-08-27 Hitachi, Ltd. Semiconductor integrated circuit device
JPH0212445A (ja) * 1988-06-30 1990-01-17 Mitsubishi Electric Corp 記憶装置
DE3911999A1 (de) * 1989-04-12 1990-10-18 Philips Patentverwaltung Uebertragungssystem
US5448583A (en) * 1989-08-28 1995-09-05 Fujitsu Limited Apparatus and method using analog viterbi decoding techniques
US5027374A (en) * 1990-03-26 1991-06-25 Motorola, Inc. Bit serial Viterbi decoder add/compare/select array
JP2594683B2 (ja) * 1990-05-18 1997-03-26 三菱電機株式会社 ヴィタビ・デコーダ
JP2693256B2 (ja) * 1990-05-25 1997-12-24 富士通株式会社 記録装置用ビタビ等化器及び記録装置
US5263052A (en) * 1991-09-30 1993-11-16 Motorola, Inc. Viterbi equalizer for radio receiver
US5377133A (en) * 1992-04-07 1994-12-27 Digital Equipment Corporation System for enhanced implementation of add-compare-select (ACS) functions
US5432803A (en) * 1992-04-30 1995-07-11 Novatel Communications, Ltd. Maximum likelihood convolutional decoder
US5255343A (en) * 1992-06-26 1993-10-19 Northern Telecom Limited Method for detecting and masking bad frames in coded speech signals
US5424881A (en) 1993-02-01 1995-06-13 Cirrus Logic, Inc. Synchronous read channel
US5349608A (en) * 1993-03-29 1994-09-20 Stanford Telecommunications, Inc. Viterbi ACS unit with renormalization
JPH06338808A (ja) * 1993-05-28 1994-12-06 Matsushita Electric Ind Co Ltd 加算比較選択装置
US5432804A (en) * 1993-11-16 1995-07-11 At&T Corp. Digital processor and viterbi decoder having shared memory
US6002538A (en) * 1994-03-18 1999-12-14 Fujitsu, Ltd. PRML regenerating apparatus having adjusted slice levels
AU2035800A (en) * 1999-12-02 2001-06-12 Johns Hopkins University, The Apparatus for and method of implementing viterbi decoding
CN100454764C (zh) * 2002-10-30 2009-01-21 联发科技股份有限公司 存活路径存储器电路及使用该电路的维特比解码器
TWI245496B (en) * 2004-07-14 2005-12-11 Lite On It Corp Method for determining output signals of a Viterbi decoder
CN100466480C (zh) * 2004-07-23 2009-03-04 建兴电子科技股份有限公司 一种决定维特比解码器的输出信号的方法及其输出选择器
US8059745B2 (en) * 2008-08-06 2011-11-15 Texas Instruments Incorporated Sharing logic circuitry for a maximum likelihood MIMO decoder and a viterbi decoder
US8595576B2 (en) * 2011-06-30 2013-11-26 Lsi Corporation Systems and methods for evaluating and debugging LDPC iterative decoders

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4240156A (en) * 1979-03-29 1980-12-16 Doland George D Concatenated error correcting system
JPS6081925A (ja) * 1983-10-12 1985-05-10 Nec Corp 誤り訂正装置
JPS60173930A (ja) * 1984-02-20 1985-09-07 Fujitsu Ltd パイプライン処理ビタビ復号器
JPS60180222A (ja) * 1984-02-27 1985-09-14 Nec Corp 符号誤り訂正装置
US4680761A (en) * 1986-01-30 1987-07-14 Burkness Donald C Self diagnostic Cyclic Analysis Testing System (CATS) for LSI/VLSI

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10217043A1 (de) * 2002-04-17 2003-11-06 Infineon Technologies Ag Verfahren und Einrichtung zum Testen eines Pfadgedächtnisspeichers des Registeraustausch-Typs sowie testfähiger Pfadgedächtnisspeicher

Also Published As

Publication number Publication date
DE3687401D1 (de) 1993-02-11
JPS62101128A (ja) 1987-05-11
EP0221507B1 (en) 1992-12-30
EP0221507A3 (en) 1989-01-18
US4763328A (en) 1988-08-09
EP0221507A2 (en) 1987-05-13
CA1272290A (en) 1990-07-31
JPH029487B2 (cg-RX-API-DMAC7.html) 1990-03-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee